coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50454 ) Change subject: soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/cezanne/fch.c: https://review.coreboot.org/c/coreboot/+/50454/comment/4c669ac9_997758ba PS3, Line 28: : /* : * SMI on SlpTyp requires sending SMI before completion : * response of the I/O write. The BKDG also specifies : * clearing ForceStpClkRetry for SMI trapping. : */ > i'll look into it Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114 Gerrit-Change-Number: 50454 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 19:18:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50318 ) Change subject: src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0 ...................................................................... src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0 Change-Id: I7cc47536b0c1e2c903df29402090abfccde82406 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50318 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/ec/quanta/ene_kb3940q/acpi/battery.asl 1 file changed, 30 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/ec/quanta/ene_kb3940q/acpi/battery.asl b/src/ec/quanta/ene_kb3940q/acpi/battery.asl index 09c1b29..517fba7 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/battery.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/battery.asl @@ -39,18 +39,18 @@ }) // Workaround for full battery status, enabled by default - Name (BFWK, One) + Name (BFWK, 1) // Method to enable full battery workaround Method (BFWE) { - Store (One, BFWK) + BFWK = 1 } // Method to disable full battery workaround Method (BFWD) { - Store (Zero, BFWK) + BFWK = 0 } // Device insertion/removal control method that returns a device's status. @@ -68,18 +68,18 @@ Method (_BIF, 0, Serialized) { // Update fields from EC - Store (BDC0, Index (PBIF, 1)) // Batt Design Capacity - Store (BFC0, Index (PBIF, 2)) // Batt Last Full Charge Capacity - Store (BDV0, Index (PBIF, 4)) // Batt Design Voltage - Divide(BFC0, 0x64, , Local1) - Multiply(Local1, 0x0A, Local0) - Store(Local0, Index(PBIF, 5)) - Multiply(Local1, 0x05, Local0) - Store (Local0, Index (PBIF, 6)) - Store (ToString(Concatenate(BATD, 0x00)), Index (PBIF, 9)) // Model Number - Store (ToDecimalString(BSN0), Index (PBIF, 10)) // Serial Number - Store (ToString(Concatenate(BCHM, 0x00)), Index (PBIF, 11)) // Battery Type - Store (\BATV, Index (PBIF, 12)) // OEM information + PBIF [1] = BDC0 // Batt Design Capacity + PBIF [2] = BFC0 // Batt Last Full Charge Capacity + PBIF [4] = BDV0 // Batt Design Voltage + Local1 = BFC0 / 100 + Local0 = Local1 * 10 + PBIF [5] = Local0 + Local0 = Local1 * 5 + PBIF [6] = Local0 + PBIF [9] = ToString(Concatenate(BATD, 0x00)) // Model Number + PBIF [10] = ToDecimalString(BSN0) // Serial Number + PBIF [11] = ToString(Concatenate(BCHM, 0x00)) // Battery Type + PBIF [12] = \BATV // OEM information Return (PBIF) } @@ -95,45 +95,44 @@ // // Get battery state from EC - Store (BST0, Local0) - Store (Local0, Index (PBST, 0)) + Local0 = BST0 + PBST [0] = Local0 // // 1: BATTERY PRESENT RATE/CURRENT // - Store (BPC0, Local1) - If (LAnd (Local1, 0x8000)) { - Xor (Local1, 0xFFFF, Local1) - Increment (Local1) + Local1 = BPC0 + If (Local1 && 0x8000) { + Local1 ^= 0xffff + Local1++ } - Store (Local1, Index (PBST, 1)) + PBST [1] = Local1 // // 2: BATTERY REMAINING CAPACITY // - Store (BRC0, Local1) + Local1 = BRC0 - If (LAnd (BFWK, LAnd (ADPT, LNot (Local0)))) { + If (BFWK && ADPT && !Local0) { // On AC power and battery is neither charging // nor discharging. Linux expects a full battery // to report same capacity as last full charge. // https://bugzilla.kernel.org/show_bug.cgi?id=12632 - Store (BFC0, Local2) + Local2 = BFC0 // See if within ~3% of full - ShiftRight (Local2, 5, Local3) - If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) + Local3 = Local2 >> 5 + If (Local1 > (Local2 - Local3) && Local1 < (Local2 + Local3)) { - Store (Local2, Local1) + Local1 = Local2 } } - Store (Local1, Index (PBST, 2)) + PBST [2] = Local1 // // 3: BATTERY PRESENT VOLTAGE // - Store (BPV0, Index (PBST, 3)) + PBST [3] = BPV0 Return (PBST) } -- To view, visit https://review.coreboot.org/c/coreboot/+/50318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cc47536b0c1e2c903df29402090abfccde82406 Gerrit-Change-Number: 50318 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: HAOUAS Elyes. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50318 ) Change subject: src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cc47536b0c1e2c903df29402090abfccde82406 Gerrit-Change-Number: 50318 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 10 Feb 2021 19:18:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/smihandler: use size_t and unsigned int
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50486 ) Change subject: soc/amd/*/smihandler: use size_t and unsigned int ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50486/comment/29103d30_0f076cda PS1, Line 10: cases the value shouldn't became negative. > I agree with what you're saying, but why not use an unsigned int instead of a size? The core number […] yeah, for the core variable that's a bit more intuitive -- To view, visit https://review.coreboot.org/c/coreboot/+/50486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba Gerrit-Change-Number: 50486 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 19:18:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50317 ) Change subject: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0 ...................................................................... src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0 Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50317 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/ec/lenovo/h8/acpi/battery.asl 1 file changed, 43 insertions(+), 41 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index 42b91b9..d5e8c12 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -80,7 +80,7 @@ */ Method(BPAG, 1, NotSerialized) { - Store(Arg0, PAGE) + PAGE = Arg0 #ifdef BATTERY_PAGE_DELAY_MS Sleep(BATTERY_PAGE_DELAY_MS) #endif @@ -94,32 +94,32 @@ Method(BSTA, 4, NotSerialized) { Acquire(ECLK, 0xffff) - Store(0, Local0) - ^BPAG(Or(1, Arg0)) - Store(BAMA, Local1) + Local0 = 0 + ^BPAG(Arg0 | 1) + Local1 = BAMA ^BPAG(Arg0) /* Battery dynamic information */ /* * Present rate is a 16bit signed int, positive while charging * and negative while discharging. */ - Store(BAPR, Local2) + Local2 = BAPR If (Arg2) // Charging { - Or(2, Local0, Local0) + Local0 |= 2 } Else { If (Arg3) // Discharging { - Or(1, Local0, Local0) + Local0 |= 1 // Negate present rate - Subtract(0x10000, Local2, Local2) + Local2 -= 0x10000 } Else // Full battery, force to 0 { - Store(0, Local2) + Local2 = 0 } } @@ -127,21 +127,21 @@ * The present rate value must be positive now, if it is not we have an * EC bug or inconsistency and force the value to 0. */ - If (LGreaterEqual (Local2, 0x8000)) { - Store(0, Local2) + If (Local2 >= 0x8000) { + Local2 = 0 } - Store(Local0, Index(Arg1, 0x00)) + Arg1 [0] = Local0 if (Local1) { - Multiply (BARC, 10, Index(Arg1, 2)) - Multiply (Local2, BAVO, Local2) - Divide (Local2, 1000, , Index(Arg1, 1)) + Arg1 [2] = BARC * 10 + Local2 *= BAVO + Arg1 [1] = Local2 / 1000 } else { - Store(BARC, Index(Arg1, 2)) - Store(Local2, Index(Arg1, 1)) + Arg1 [2] = BARC + Arg1 [1] = Local2 } - Store(BAVO, Index(Arg1, 3)) + Arg1 [3] = BAVO Release(ECLK) Return (Arg1) } @@ -150,43 +150,45 @@ { Acquire(ECLK, 0xffff) ^BPAG(Or(1, Arg1)) /* Battery 0 static information */ - Xor(BAMA, 1, Index(Arg0, 0)) - Store(BAMA, Local0) + Arg0 [0] = BAMA ^ 1 + Local0 = BAMA ^BPAG(Arg1) - Store(BAFC, Local2) - ^BPAG(Or(2, Arg1)) - Store(BADC, Local1) + Local2 = BAFC + ^BPAG(Arg1 | 2) + Local1 = BADC if (Local0) { - Multiply (Local1, 10, Local1) - Multiply (Local2, 10, Local2) + Local1 *= 10 + Local2 *= 10 } - Store(Local1, Index(Arg0, 1)) // Design Capacity - Store(Local2, Index(Arg0, 2)) // Last full charge capacity - Store(BADV, Index(Arg0, 4)) // Design Voltage - Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity + Arg0 [1] = Local1 // Design Capacity + Arg0 [2] = Local2 // Last full charge capacity + Arg0 [4] = BADV // Design Voltage + Local0 = Local2 % 20 // FIXME: Local0 not used + Arg0 [5] = Local2 / 20 // Warning capacity - Store (BASN, Local0) + Local0 = BASN Name (SERN, Buffer (0x06) { " " }) - Store (4, Local1) + Local1 = 4 While (Local0) { - Divide (Local0, 0x0A, Local2, Local0) - Add (Local2, 48, Index (SERN, Local1)) - Decrement (Local1) + Local2 = Local0 % 10 + Local0 /= 10 + SERN [Local1] = Local2 + 48 + Local1-- } - Store (SERN, Index (Arg0, 10)) // Serial Number + Arg0 [10] = SERN // Serial Number ^BPAG(Or(4, Arg1)) Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) - Store(BATY, TYPE) - Store(TYPE, Index (Arg0, 11)) // Battery type - ^BPAG(Or(5, Arg1)) - Store(BAOE, Index (Arg0, 12)) // OEM information - ^BPAG(Or(6, Arg1)) - Store(BANA, Index (Arg0, 9)) // Model number + TYPE = BATY + Arg0 [11] = TYPE // Battery type + ^BPAG(Arg1 | 5) + Arg0 [12] = BAOE // OEM information + ^BPAG(Arg1 | 6) + Arg0 [9] = BANA // Model number Release(ECLK) Return (Arg0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/50317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60 Gerrit-Change-Number: 50317 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Alexander Couzens, HAOUAS Elyes. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50317 ) Change subject: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60 Gerrit-Change-Number: 50317 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 10 Feb 2021 19:17:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/fch: remove comment about ForceStpClkRetry
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50495 ) Change subject: soc/amd/picasso/fch: remove comment about ForceStpClkRetry ...................................................................... soc/amd/picasso/fch: remove comment about ForceStpClkRetry The corresponding bit is marked as reserved in the PPR. Also there's no BKDG for Picasso any more; the BKDG was mostly replaced by the PPR. Also fix the style of the comment. Change-Id: Iffdbb9e951cb140e4352ab0f198f72a71ba798dc Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/fch.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/50495/1 diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 5d62e8e..e52090a 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -135,9 +135,7 @@ configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); /* SMI on SlpTyp requires sending SMI before completion - * response of the I/O write. The BKDG also specifies - * clearing ForceStpClkRetry for SMI trapping. - */ + response of the I/O write. */ reg = pm_read32(PM_PCI_CTRL); reg |= FORCE_SLPSTATE_RETRY; pm_write32(PM_PCI_CTRL, reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/50495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffdbb9e951cb140e4352ab0f198f72a71ba798dc Gerrit-Change-Number: 50495 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: select soc-specific APCI functionality
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50487 to look at the new patch set (#2). Change subject: soc/amd/cezanne: select soc-specific APCI functionality ...................................................................... soc/amd/cezanne: select soc-specific APCI functionality This doesn't select HAVE_ACPI_TABLES, so no ACPI tables will be generated for now. There's also no globalnvs.asl that corresponds to nvs.h yet. Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/include/soc/nvs.h M src/soc/amd/cezanne/include/soc/southbridge.h 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/50487/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Gerrit-Change-Number: 50487 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/*/smihandler: use size_t and unsigned int
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50486 to look at the new patch set (#2). Change subject: soc/amd/*/smihandler: use size_t and unsigned int ...................................................................... soc/amd/*/smihandler: use size_t and unsigned int signed int should only be used when we need negative values and in those cases the value shouldn't became negative. Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c 2 files changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/50486/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba Gerrit-Change-Number: 50486 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd: include cpu/x86/smm directory in common SMM Makefile
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Martin Roth, Patrick Georgi, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50464 to look at the new patch set (#4). Change subject: soc/amd: include cpu/x86/smm directory in common SMM Makefile ...................................................................... soc/amd: include cpu/x86/smm directory in common SMM Makefile Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id6be7aa7f295e61f873bfae1fca42260d3b0db78 --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/block/cpu/smm/Makefile.inc M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc 4 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/50464/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6be7aa7f295e61f873bfae1fca42260d3b0db78 Gerrit-Change-Number: 50464 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2021