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Change subject: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0
......................................................................
Patch Set 2:
(1 comment)
File src/ec/lenovo/h8/acpi/battery.asl:
https://review.coreboot.org/c/coreboot/+/50317/comment/6d552851_3ff31e6d
PS1, Line 130: >
> >=
Thank you.
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Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50494 )
Change subject: util/abuild: Ensure that non-Chrome OS builds are non-Chrome OS
......................................................................
util/abuild: Ensure that non-Chrome OS builds are non-Chrome OS
Sometimes boards enable it by default, making the Kconfig option
impossible to disable without messing with the Kconfig files. This
shouldn't happen, so report on such occurrences early.
TEST=Tried building GOOGLE_KOHAKU through abuild with -x, without
-x and both cases after having added a "select CHROMEOS" for testing
and it failed in the "without -x with select" scenario while properly
configuring and passing all other builds.
Change-Id: Ieb6bcbf3e9ca8cd4ced85c7c9ffaa39505f5a9b7
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M util/abuild/abuild
1 file changed, 22 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50494/1
diff --git a/util/abuild/abuild b/util/abuild/abuild
index 408de12..a0d4129 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -330,14 +330,23 @@
local BUILD_DIR="$1"
local TEST_TYPE="$2"
local TEST_STRING="$3"
+ local NEGATE="$4"
local CONFIG_FILE="$BUILD_DIR/config.build"
local CONFIG_LOG="$BUILD_DIR/config.log"
- if ! grep -q "$TEST_STRING" "$CONFIG_FILE"; then
- echo "config file: $CONFIG_FILE has incorrect $TEST_TYPE"
- echo "Error: Expected '$TEST_STRING' in config file." >> "$CONFIG_LOG"
- return 1
+ if [ -z "$NEGATE" ]; then
+ if ! grep -q "$TEST_STRING" "$CONFIG_FILE"; then
+ echo "config file: $CONFIG_FILE has incorrect $TEST_TYPE"
+ echo "Error: Expected '$TEST_STRING' in config file." >> "$CONFIG_LOG"
+ return 1
+ fi
+ else
+ if grep -q "$TEST_STRING" "$CONFIG_FILE"; then
+ echo "config file: $CONFIG_FILE has incorrect $TEST_TYPE"
+ echo "Error: Expected not to see '$TEST_STRING' in config file." >> "$CONFIG_LOG"
+ return 1
+ fi
fi
return 0
@@ -443,7 +452,15 @@
check_config "$build_dir" "vendor" "CONFIG_VENDOR_$(mainboard_vendor "${MAINBOARD}")=y"
local VENDOR_OK=$?
- if [ $BUILDENV_CREATED -ne 0 ] || [ $MAINBOARD_OK -ne 0 ] || [ $VENDOR_OK -ne 0 ]; then
+
+ if [ "$chromeos" = false ]; then
+ check_config "$build_dir" "Chrome OS" "CONFIG_CHROMEOS=y" negate
+ local FORCE_ENABLED_CROS=$?
+ else
+ local FORCE_ENABLED_CROS=0
+ fi
+
+ if [ $BUILDENV_CREATED -ne 0 ] || [ $MAINBOARD_OK -ne 0 ] || [ $VENDOR_OK -ne 0 ] || [ $FORCE_ENABLED_CROS -eq 1 ]; then
junit " <testcase classname='board${testclass/#/.}' name='$BUILD_NAME' >"
junit "<failure type='BuildFailed'>"
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Change subject: src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
Thx
File src/ec/quanta/ene_kb3940q/acpi/battery.asl:
https://review.coreboot.org/c/coreboot/+/50318/comment/1c01ec20_9fb83c7b
PS1, Line 42: One
> 1
Done
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Change subject: soc/intel/*: Update microcode as specified for MP-init
......................................................................
Patch Set 13:
(1 comment)
File src/soc/intel/alderlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/49899/comment/4edc4491_3b91d460
PS13, Line 70: PRMRR
> For ADL, there is a new MCHECK flow in the FSP, which apparently requires a microcode load immediate […]
for CML: it doesn't mention it explicitly, but I reads as SMRR is updated with MTRR, PRMRR and DCU mode in Phase 3. SMRR is only written in SMM which would match the comment.
For Icelake/Tigerlake it says:
Must reload after memory initialization and PRMRR are configured.
PRMRR isn't currently configured on those platforms, so a second microcode update isn't required at all?
Should I remove the second microcode update from all platforms using CpuMpPpi? That is Icelake+ ?
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Change subject: util/superiotool: Add ITE IT8616E/IT8656E support
......................................................................
Patch Set 1: Code-Review+2
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Angel Pons, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/amd/majolica: Add chromeos support
......................................................................
mb/amd/majolica: Add chromeos support
This change enables vboot support. To use it add CHROMEOS=y to your
config.
TEST=Boot majolica and see verstage run, and then see depthcharge load.
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 verstage starting (log level: 8)...
Phase 1
FMAP: area GBB found @ 805000 (458752 bytes)
VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
Phase 2
Phase 3
FMAP: area GBB found @ 805000 (458752 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_keyblock() Checking keyblock signature...
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_fw_preamble() Verifying preamble.
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Phase 4
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
VB2:vb2api_init_hash() HW crypto forbidden by TPM flag, using SW
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Saving secdata firmware
Saving secdata kernel
Saving nvdata
Slot A is selected
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: mcache @0x02017000 built for 9 files, used 0x1ec of 0x800 bytes
CBFS: Found 'fallback/romstage' @0x0 size 0x753c in mcache @0x02017000
BS: verstage times (exec / console): total (unknown) / 116 ms
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 romstage starting (log level: 8)...
Family_Model: 00a50f00
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: Found 'fspm.bin' @0x15440 size 0x2257d in mcache @0x02017138
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1
---
M src/mainboard/amd/majolica/Kconfig
M src/mainboard/amd/majolica/chromeos.fmd
2 files changed, 45 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/50343/4
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Change subject: soc/amd/cezanne: Add verstage support
......................................................................
soc/amd/cezanne: Add verstage support
Setup the config required to support verstage.
The offsets are the same as picasso.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/50342/4
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Change subject: mb/amd/majolica: Add chromeos support
......................................................................
mb/amd/majolica: Add chromeos support
This change enables vboot support. To use it add CHROMEOS=y to your
config.
TEST=Boot majolica and see verstage run, and then see depthcharge load.
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 verstage starting (log level: 8)...
Phase 1
FMAP: area GBB found @ 805000 (458752 bytes)
VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
Phase 2
Phase 3
FMAP: area GBB found @ 805000 (458752 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_keyblock() Checking keyblock signature...
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_fw_preamble() Verifying preamble.
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Phase 4
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
VB2:vb2api_init_hash() HW crypto forbidden by TPM flag, using SW
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Saving secdata firmware
Saving secdata kernel
Saving nvdata
Slot A is selected
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: mcache @0x02017000 built for 9 files, used 0x1ec of 0x800 bytes
CBFS: Found 'fallback/romstage' @0x0 size 0x753c in mcache @0x02017000
BS: verstage times (exec / console): total (unknown) / 116 ms
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 romstage starting (log level: 8)...
Family_Model: 00a50f00
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: Found 'fspm.bin' @0x15440 size 0x2257d in mcache @0x02017138
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1
---
M src/mainboard/amd/majolica/Kconfig
M src/mainboard/amd/majolica/chromeos.fmd
2 files changed, 45 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/50343/3
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