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Change in coreboot[master]: soc/amd: factor out common SMM relocation code
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50462 ) Change subject: soc/amd: factor out common SMM relocation code ...................................................................... soc/amd: factor out common SMM relocation code The common code gets moved to soc/amd/common/block/cpu/smm, since it is related to the CPU cores and soc/amd/common/block/smi is about the SMI/ SCI functionality in the FCH part. Also relocation_handler gets renamed to smm_relocation_handler to keep it clear what it does, since it got moved to another compilation unit. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/cpu/Kconfig A src/soc/amd/common/block/cpu/smm/Makefile.inc A src/soc/amd/common/block/cpu/smm/smm_relocate.c A src/soc/amd/common/block/include/amdblocks/smm.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/cpu.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/cpu.c 9 files changed, 79 insertions(+), 96 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 4949286..2de60d7 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -32,6 +32,7 @@ select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SMM select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index c155975..996605e 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -28,6 +28,12 @@ endif # SOC_AMD_COMMON_BLOCK_NONCAR +config SOC_AMD_COMMON_BLOCK_SMM + bool + default n + help + Add common SMM relocation and handler functionality to the build. + config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H bool select COLLECT_TIMESTAMPS_NO_TSC # selected use SoC-specific timestamp function diff --git a/src/soc/amd/common/block/cpu/smm/Makefile.inc b/src/soc/amd/common/block/cpu/smm/Makefile.inc new file mode 100644 index 0000000..0639890 --- /dev/null +++ b/src/soc/amd/common/block/cpu/smm/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMM),y) + +ramstage-y += smm_relocate.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c new file mode 100644 index 0000000..1d7cc68 --- /dev/null +++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/smm.h> +#include <console/console.h> +#include <cpu/amd/amd64_save_state.h> +#include <cpu/amd/msr.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> +#include <types.h> + +static struct smm_relocation_params smm_reloc_params; + +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + smm_region(&tseg_base, &tseg_size); + + params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB); + params->tseg_base.hi = 0; + params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB); + params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); + + params->tseg_mask.lo |= SMM_TSEG_WB; +} + +void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); +} + +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) +{ + struct smm_relocation_params *relo_params = &smm_reloc_params; + amd64_smm_state_save_area_t *smm_state; + + wrmsr(SMM_ADDR_MSR, relo_params->tseg_base); + wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); + + smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); + smm_state->smbase = staggered_smbase; +} diff --git a/src/soc/amd/common/block/include/amdblocks/smm.h b/src/soc/amd/common/block/include/amdblocks/smm.h new file mode 100644 index 0000000..0fbef42 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/smm.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/msr.h> +#include <types.h> + +struct smm_relocation_params { + msr_t tseg_base; + msr_t tseg_mask; +}; + +void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4868d84..f504d09 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -42,6 +42,7 @@ select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SMM select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 8ee065d..088660e 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/cpu.h> +#include <amdblocks/smm.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/amd/msr.h> -#include <cpu/amd/amd64_save_state.h> #include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> @@ -22,12 +21,6 @@ /* * MP and SMM loading initialization. */ -struct smm_relocation_params { - msr_t tseg_base; - msr_t tseg_mask; -}; - -static struct smm_relocation_params smm_reloc_params; /* * Do essential initialization tasks before APs can be fired up - @@ -42,45 +35,6 @@ x86_mtrr_check(); } -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - smm_region(&tseg_base, &tseg_size); - - params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB); - params->tseg_base.hi = 0; - params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB); - params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); - - params->tseg_mask.lo |= SMM_TSEG_WB; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); -} - -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - amd64_smm_state_save_area_t *smm_state; - - wrmsr(SMM_ADDR_MSR, relo_params->tseg_base); - wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); - - smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - static void post_mp_init(void) { global_smi_enable(); @@ -91,7 +45,7 @@ .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, - .relocation_handler = relocation_handler, + .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, }; diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b400e1b..728e063 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -41,6 +41,7 @@ select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SMM select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_UART select SSE2 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 9992fc5..badea8b 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/smm.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/amd/msr.h> -#include <cpu/amd/amd64_save_state.h> #include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> @@ -21,12 +20,6 @@ /* * MP and SMM loading initialization. */ -struct smm_relocation_params { - msr_t tseg_base; - msr_t tseg_mask; -}; - -static struct smm_relocation_params smm_reloc_params; /* * Do essential initialization tasks before APs can be fired up - @@ -47,50 +40,11 @@ + 1; } -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - smm_region(&tseg_base, &tseg_size); - - params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB); - params->tseg_base.hi = 0; - params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB); - params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); - - params->tseg_mask.lo |= SMM_TSEG_WB; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); -} - -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - amd64_smm_state_save_area_t *smm_state; - - wrmsr(SMM_ADDR_MSR, relo_params->tseg_base); - wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); - - smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, - .relocation_handler = relocation_handler, + .relocation_handler = smm_relocation_handler, .post_mp_init = global_smi_enable, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/50462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb Gerrit-Change-Number: 50462 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Add PCI IRQ Router definitions
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50451 ) Change subject: soc/amd/cezanne: Add PCI IRQ Router definitions ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h: https://review.coreboot.org/c/coreboot/+/50451/comment/c54df3bf_dc554e82 PS1, Line 61: #define PIRQ_UART2 0x78 /* UART2 */ : #define PIRQ_UART3 0x79 /* UART3 */ > I'm using 56569-A1 Rev 3. […] oh, turns out that i didn't hit submit on that change request; at least i don't find a confirmation email. in rev 3.01 at least in the memory mapping tables there are only uart0 and uart1 and i'm pretty sure that 2 and 3 don't exist in cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/50451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e Gerrit-Change-Number: 50451 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 01:10:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Fix missing header in amd_pci_utils.h
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

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Change in coreboot[master]: soc/amd*/smihandler: factor out and rename clear_smi_sci_status
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50460 ) Change subject: soc/amd*/smihandler: factor out and rename clear_smi_sci_status ...................................................................... soc/amd*/smihandler: factor out and rename clear_smi_sci_status Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifd6c3bebee1ccf7e7e7987d8ae3d9fa654019791 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50460 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/include/amdblocks/smi.h M src/soc/amd/common/block/smi/smi_util.c M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c 4 files changed, 10 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/smi.h b/src/soc/amd/common/block/include/amdblocks/smi.h index 25a1da7..97edd2c 100644 --- a/src/soc/amd/common/block/include/amdblocks/smi.h +++ b/src/soc/amd/common/block/include/amdblocks/smi.h @@ -48,5 +48,6 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); void clear_all_smi_status(void); +void clear_smi_sci_status(void); #endif /* AMD_BLOCK_SMI_H */ diff --git a/src/soc/amd/common/block/smi/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c index aa37dab..b763c3b 100644 --- a/src/soc/amd/common/block/smi/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -154,3 +154,8 @@ smi_write32(SMI_REG_SMISTS3, smi_read32(SMI_REG_SMISTS3)); smi_write32(SMI_REG_SMISTS4, smi_read32(SMI_REG_SMISTS4)); } + +void clear_smi_sci_status(void) +{ + smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); +} diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 5134358..626daad 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -222,14 +222,6 @@ { .type = SMITYPE_SLP_TYP, .handler = sb_slp_typ_handler}, }; -static void process_smi_sci(void) -{ - const uint32_t status = smi_read32(SMI_SCI_STATUS); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(SMI_SCI_STATUS, status); -} - static void *get_source_handler(int source) { int i; @@ -270,7 +262,8 @@ const uint16_t smi_src = smi_read16(SMI_REG_POINTER); if (smi_src & SMI_STATUS_SRC_SCI) - process_smi_sci(); + /* Clear events to prevent re-entering SMI if event isn't handled */ + clear_smi_sci_status(); if (smi_src & SMI_STATUS_SRC_0) process_smi_sources(SMI_REG_SMISTS0); if (smi_src & SMI_STATUS_SRC_1) diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index e90bdb1..ffcbaea 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -217,14 +217,6 @@ { .type = SMITYPE_SLP_TYP, .handler = sb_slp_typ_handler}, }; -static void process_smi_sci(void) -{ - const uint32_t status = smi_read32(SMI_SCI_STATUS); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(SMI_SCI_STATUS, status); -} - static void *get_source_handler(int source) { int i; @@ -265,7 +257,8 @@ const uint16_t smi_src = smi_read16(SMI_REG_POINTER); if (smi_src & SMI_STATUS_SRC_SCI) - process_smi_sci(); + /* Clear events to prevent re-entering SMI if event isn't handled */ + clear_smi_sci_status(); if (smi_src & SMI_STATUS_SRC_0) process_smi_sources(SMI_REG_SMISTS0); if (smi_src & SMI_STATUS_SRC_1) -- To view, visit https://review.coreboot.org/c/coreboot/+/50460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd6c3bebee1ccf7e7e7987d8ae3d9fa654019791 Gerrit-Change-Number: 50460 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd*/smihandler: factor out and rename clear_all_smi_status
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50459 ) Change subject: soc/amd*/smihandler: factor out and rename clear_all_smi_status ...................................................................... soc/amd*/smihandler: factor out and rename clear_all_smi_status The old name was misleading, since it doesn't disable the generation of SMIs, but clears the status registers. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/include/amdblocks/smi.h M src/soc/amd/common/block/smi/smi_util.c M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c 4 files changed, 14 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/smi.h b/src/soc/amd/common/block/include/amdblocks/smi.h index 31f9042..25a1da7 100644 --- a/src/soc/amd/common/block/include/amdblocks/smi.h +++ b/src/soc/amd/common/block/include/amdblocks/smi.h @@ -47,5 +47,6 @@ void disable_gevent_smi(uint8_t gevent); void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); +void clear_all_smi_status(void); #endif /* AMD_BLOCK_SMI_H */ diff --git a/src/soc/amd/common/block/smi/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c index e3379f3..aa37dab 100644 --- a/src/soc/amd/common/block/smi/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -143,3 +143,14 @@ { return pm_read16(PM_ACPI_SMI_CMD); } + +void clear_all_smi_status(void) +{ + smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); + smi_write32(SMI_EVENT_STATUS, smi_read32(SMI_EVENT_STATUS)); + smi_write32(SMI_REG_SMISTS0, smi_read32(SMI_REG_SMISTS0)); + smi_write32(SMI_REG_SMISTS1, smi_read32(SMI_REG_SMISTS1)); + smi_write32(SMI_REG_SMISTS2, smi_read32(SMI_REG_SMISTS2)); + smi_write32(SMI_REG_SMISTS3, smi_read32(SMI_REG_SMISTS3)); + smi_write32(SMI_REG_SMISTS4, smi_read32(SMI_REG_SMISTS4)); +} diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index d6c3ed0..5134358 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -123,17 +123,6 @@ mainboard_smi_apmc(cmd); } -static void disable_all_smi_status(void) -{ - smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); - smi_write32(SMI_EVENT_STATUS, smi_read32(SMI_EVENT_STATUS)); - smi_write32(SMI_REG_SMISTS0, smi_read32(SMI_REG_SMISTS0)); - smi_write32(SMI_REG_SMISTS1, smi_read32(SMI_REG_SMISTS1)); - smi_write32(SMI_REG_SMISTS2, smi_read32(SMI_REG_SMISTS2)); - smi_write32(SMI_REG_SMISTS3, smi_read32(SMI_REG_SMISTS3)); - smi_write32(SMI_REG_SMISTS4, smi_read32(SMI_REG_SMISTS4)); -} - static void sb_slp_typ_handler(void) { uint32_t pci_ctrl, reg32; @@ -172,7 +161,7 @@ wbinvd(); - disable_all_smi_status(); + clear_all_smi_status(); /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */ pci_ctrl = pm_read32(PM_PCI_CTRL); diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 45dd07d..e90bdb1 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -118,17 +118,6 @@ mainboard_smi_apmc(cmd); } -static void disable_all_smi_status(void) -{ - smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); - smi_write32(SMI_EVENT_STATUS, smi_read32(SMI_EVENT_STATUS)); - smi_write32(SMI_REG_SMISTS0, smi_read32(SMI_REG_SMISTS0)); - smi_write32(SMI_REG_SMISTS1, smi_read32(SMI_REG_SMISTS1)); - smi_write32(SMI_REG_SMISTS2, smi_read32(SMI_REG_SMISTS2)); - smi_write32(SMI_REG_SMISTS3, smi_read32(SMI_REG_SMISTS3)); - smi_write32(SMI_REG_SMISTS4, smi_read32(SMI_REG_SMISTS4)); -} - static void sb_slp_typ_handler(void) { uint32_t pci_ctrl, reg32; @@ -167,7 +156,7 @@ wbinvd(); - disable_all_smi_status(); + clear_all_smi_status(); /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */ pci_ctrl = pm_read32(PM_PCI_CTRL); -- To view, visit https://review.coreboot.org/c/coreboot/+/50459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce Gerrit-Change-Number: 50459 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: add empty SMM-handler
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50455 ) Change subject: soc/amd/cezanne: add empty SMM-handler ...................................................................... soc/amd/cezanne: add empty SMM-handler Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I95908fac3b1e17a16542e5d80001fac3d22d839a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50455 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/smihandler.c 3 files changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 10c085e..4949286 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -17,6 +17,7 @@ select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA select HAVE_CF9_RESET + select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select IOAPIC select PLATFORM_USES_FSP2_0 @@ -154,6 +155,19 @@ default 0xfedc9000 if UART_FOR_CONSOLE = 0 default 0xfedca000 if UART_FOR_CONSOLE = 1 +config SMM_TSEG_SIZE + hex + default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER + default 0x0 + +config SMM_RESERVED_SIZE + hex + default 0x180000 + +config SMM_MODULE_STACK_SIZE + hex + default 0x800 + menu "PSP Configuration Options" config AMD_FWM_POSITION_INDEX diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index ce9f66c..3501282 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -4,6 +4,7 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm # Beware that all-y also adds the compilation unit to verstage on PSP all-y += config.c @@ -34,6 +35,8 @@ ramstage-y += root_complex.c ramstage-y += uart.c +smm-y += smihandler.c + CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c new file mode 100644 index 0000000..2d9e487 --- /dev/null +++ b/src/soc/amd/cezanne/smihandler.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/smm.h> + +void southbridge_smi_handler(void) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/50455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95908fac3b1e17a16542e5d80001fac3d22d839a Gerrit-Change-Number: 50455 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/stoneyridge: drop empty sb_enable
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50437 ) Change subject: soc/amd/stoneyridge: drop empty sb_enable ...................................................................... soc/amd/stoneyridge: drop empty sb_enable Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9b6e0bd5c7358e2f18f929d5b098d95acbf59a5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50437 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 0 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 9cae98b..f63a7c3 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -112,9 +112,6 @@ case DEVICE_PATH_CPU_CLUSTER: dev->ops = &cpu_bus_ops; break; - case DEVICE_PATH_PCI: - sb_enable(dev); - break; case DEVICE_PATH_MMIO: if (i2c_acpi_name(dev) != NULL) dev->ops = &stoneyridge_i2c_mmio_ops; diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 219af84..9480e8b 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -238,7 +238,6 @@ void enable_aoac_devices(void); void sb_clk_output_48Mhz(u32 osc); -void sb_enable(struct device *dev); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index f8a705e..161e3e8 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -352,11 +352,6 @@ fch_print_pmxc0_status(); } -void sb_enable(struct device *dev) -{ - printk(BIOS_DEBUG, "%s\n", __func__); -} - static void fch_init_acpi_ports(void) { u32 reg; -- To view, visit https://review.coreboot.org/c/coreboot/+/50437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b6e0bd5c7358e2f18f929d5b098d95acbf59a5c Gerrit-Change-Number: 50437 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: add MP init and SMM initialization
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50505 ) Change subject: soc/amd/cezanne: add MP init and SMM initialization ...................................................................... Patch Set 1: Code-Review-2 (1 comment) Patchset: PS1: this needs an fsp-side change in order to work that is still WIP, so this shouldn't be merged yet -- To view, visit https://review.coreboot.org/c/coreboot/+/50505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38d52394b5f6ffb837fa753fc9e82c0450c6aae3 Gerrit-Change-Number: 50505 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 00:23:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/majolica: Add FCH IRQ routing
by Raul Rangel (Code Review) 10 Feb '21

10 Feb '21

1 0

Change in coreboot[master]: soc/amd/cezanne: Fill FADT and MADT
by Raul Rangel (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50510 ) Change subject: soc/amd/cezanne: Fill FADT and MADT ...................................................................... soc/amd/cezanne: Fill FADT and MADT The MADT doesn't populate the IO-APICs yet since we need FSP to configure those. The FADT differs from picasso because the duty_offset is supposed to be 0. I also changed the extended to use the MMIO addresses Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4 --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/cezanne/include/soc/iomap.h 4 files changed, 115 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/50510/1 diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index c7752bf..c9f4a5f 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -3,6 +3,13 @@ /* ACPI - create the Fixed ACPI Description Tables (FADT) */ #include <acpi/acpi.h> +#include <amdblocks/acpimmio.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <types.h> +#include "chip.h" unsigned long acpi_fill_mcfg(unsigned long current) { @@ -18,7 +25,22 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* TODO */ + unsigned int i; + uint8_t irq; + uint8_t flags; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + current += acpi_create_madt_irqoverride( + (acpi_madt_irqoverride_t *)current, + MP_BUS_ISA, 0, 2, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT); + current += acpi_create_madt_irqoverride( + (acpi_madt_irqoverride_t *)current, + MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ, + MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + return current; } @@ -28,5 +50,80 @@ */ void acpi_fill_fadt(acpi_fadt_t *fadt) { - /* TODO */ + const struct soc_amd_cezanne_config *cfg = config_of_soc(); + + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); + + fadt->sci_int = ACPI_SCI_IRQ; + + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } + + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + + fadt->pm1_evt_len = 4; /* 32 bits */ + fadt->pm1_cnt_len = 2; /* 16 bits */ + fadt->pm_tmr_len = 4; /* 32 bits */ + fadt->gpe0_blk_len = 8; /* 64 bits */ + + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->duty_offset = 0; /* Not supported */ + fadt->duty_width = 0; /* Not supported */ + fadt->day_alrm = RTC_DATE_ALARM; + fadt->mon_alrm = 0; + fadt->century = RTC_ALT_CENTURY; + fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ + fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON; + fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */ + + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ + + fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ + fadt->x_firmware_ctl_h = 0; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = (u32)acpimmio_pmio + ACPI_MMIO_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = (u32)acpimmio_pmio + ACPI_MMIO_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = (u32)acpimmio_pmio + ACPI_MMIO_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = (u32)acpimmio_pmio + ACPI_MMIO_GPE0_BLK; + fadt->x_gpe0_blk.addrh = 0x0; } diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index b4e94a4..76fd444 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -7,6 +7,10 @@ struct soc_amd_cezanne_config { struct soc_amd_common_config common_config; + + /* Options for these are in src/arch/x86/include/acpi/acpi.h */ + uint16_t fadt_boot_arch; + uint32_t fadt_flags; }; #endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/include/soc/acpi.h b/src/soc/amd/cezanne/include/soc/acpi.h index 6927d93..dbcf867 100644 --- a/src/soc/amd/cezanne/include/soc/acpi.h +++ b/src/soc/amd/cezanne/include/soc/acpi.h @@ -3,5 +3,11 @@ #ifndef AMD_CEZANNE_ACPI_H #define AMD_CEZANNE_ACPI_H +#define ACPI_SCI_IRQ 9 + +/* RTC Registers */ +#define RTC_DATE_ALARM 0x0D +#define RTC_ALT_CENTURY 0x32 +#define RTC_CENTURY 0x48 #endif /* AMD_CEZANNE_ACPI_H */ diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 73640f5..509b0f7 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -29,4 +29,10 @@ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) #define SMB_BASE_ADDR 0x0b00 +#define ACPI_MMIO_BASE 0x500 +#define ACPI_MMIO_PM_EVT_BLK (ACPI_MMIO_BASE + 0x00) +#define ACPI_MMIO_PM1_CNT_BLK (ACPI_MMIO_BASE + 0x04) +#define ACPI_MMIO_PM_TMR_BLK (ACPI_MMIO_BASE + 0x08) +#define ACPI_MMIO_GPE0_BLK (ACPI_MMIO_BASE + 0x14) + #endif /* AMD_CEZANNE_IOMAP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4 Gerrit-Change-Number: 50510 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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2013

coreboot-gerrit February 2021