coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/picasso/psp: move to common code and rename to psp_smm_gen2
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50515 ) Change subject: soc/amd/picasso/psp: move to common code and rename to psp_smm_gen2 ...................................................................... soc/amd/picasso/psp: move to common code and rename to psp_smm_gen2 soc_fill_smm_trig_info and soc_fill_smm_reg_info aren't specific to Picasso. Change-Id: I771a7d36eea7307754386824190624a09c0e38f7 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/psp/Makefile.inc R src/soc/amd/common/block/psp/psp_smm_gen2.c M src/soc/amd/picasso/Makefile.inc 3 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/50515/1 diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index 907f0ef..3bb03f7 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -20,5 +20,6 @@ romstage-y += psp_gen2.c ramstage-y += psp_gen2.c smm-y += psp_gen2.c +smm-y += psp_smm_gen2.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/picasso/psp.c b/src/soc/amd/common/block/psp/psp_smm_gen2.c similarity index 100% rename from src/soc/amd/picasso/psp.c rename to src/soc/amd/common/block/psp/psp_smm_gen2.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d81eddc..e92de1f 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -25,7 +25,6 @@ romstage-y += reset.c romstage-y += memmap.c romstage-y += uart.c -romstage-y += psp.c romstage-y += mrc_cache.c verstage-y += i2c.c @@ -50,7 +49,6 @@ ramstage-y += uart.c ramstage-y += finalize.c ramstage-y += soc_util.c -ramstage-y += psp.c ramstage-y += fsp_params.c ramstage-y += update_microcode.c ramstage-y += graphics.c @@ -63,7 +61,6 @@ smm-y += uart.c endif smm-y += gpio.c -smm-y += psp.c smm-y += smu.c CPPFLAGS_common += -I$(src)/soc/amd/picasso -- To view, visit https://review.coreboot.org/c/coreboot/+/50515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I771a7d36eea7307754386824190624a09c0e38f7 Gerrit-Change-Number: 50515 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: fully commonize clear_tvalid
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50466 ) Change subject: soc/amd: fully commonize clear_tvalid ...................................................................... soc/amd: fully commonize clear_tvalid Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50466 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/common/block/cpu/smm/Makefile.inc A src/soc/amd/common/block/cpu/smm/smm_helper.c M src/soc/amd/common/block/include/amdblocks/smm.h M src/soc/amd/stoneyridge/memmap.c 5 files changed, 34 insertions(+), 44 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index 470b517..7a7f8ef 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/memmap.h> +#include <amdblocks/smm.h> #include <console/console.h> #include <cbmem.h> #include <cpu/amd/msr.h> @@ -33,28 +34,6 @@ return e; } -/* - * For data stored in TSEG, ensure TValid is clear so R/W access can reach - * the DRAM when not in SMM. - */ -static void clear_tvalid(void) -{ - msr_t hwcr = rdmsr(HWCR_MSR); - msr_t mask = rdmsr(SMM_MASK_MSR); - int tvalid = !!(mask.lo & SMM_TSEG_VALID); - - if (hwcr.lo & SMM_LOCK) { - if (!tvalid) /* not valid but locked means still accessible */ - return; - - printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); - return; - } - - mask.lo &= ~SMM_TSEG_VALID; - wrmsr(SMM_MASK_MSR, mask); -} - void smm_region(uintptr_t *start, size_t *size) { static int once; diff --git a/src/soc/amd/common/block/cpu/smm/Makefile.inc b/src/soc/amd/common/block/cpu/smm/Makefile.inc index df54d93..3008868 100644 --- a/src/soc/amd/common/block/cpu/smm/Makefile.inc +++ b/src/soc/amd/common/block/cpu/smm/Makefile.inc @@ -2,7 +2,10 @@ subdirs-y += ../../../../../../cpu/x86/smm +romstage-y += smm_helper.c +postcar-y += smm_helper.c ramstage-y += smm_relocate.c +ramstage-y += smm_helper.c smm-y += smi_handler.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/common/block/cpu/smm/smm_helper.c b/src/soc/amd/common/block/cpu/smm/smm_helper.c new file mode 100644 index 0000000..bf01b8b --- /dev/null +++ b/src/soc/amd/common/block/cpu/smm/smm_helper.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/smm.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> + +/* + * For data stored in TSEG, ensure TValid is clear so R/W access can reach + * the DRAM when not in SMM. + */ +void clear_tvalid(void) +{ + msr_t hwcr = rdmsr(HWCR_MSR); + msr_t mask = rdmsr(SMM_MASK_MSR); + int tvalid = !!(mask.lo & SMM_TSEG_VALID); + + if (hwcr.lo & SMM_LOCK) { + if (!tvalid) /* not valid but locked means still accessible */ + return; + + printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); + return; + } + + mask.lo &= ~SMM_TSEG_VALID; + wrmsr(SMM_MASK_MSR, mask); +} diff --git a/src/soc/amd/common/block/include/amdblocks/smm.h b/src/soc/amd/common/block/include/amdblocks/smm.h index 637f034..5f14b1e 100644 --- a/src/soc/amd/common/block/include/amdblocks/smm.h +++ b/src/soc/amd/common/block/include/amdblocks/smm.h @@ -11,3 +11,4 @@ void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void *get_smi_source_handler(int source); +void clear_tvalid(void); diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 32790ec..9da3e65 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/smm.h> #include <assert.h> #include <stdint.h> #include <console/console.h> @@ -56,28 +57,6 @@ return CONFIG_SMM_TSEG_SIZE; } -/* - * For data stored in TSEG, ensure TValid is clear so R/W access can reach - * the DRAM when not in SMM. - */ -static void clear_tvalid(void) -{ - msr_t hwcr = rdmsr(HWCR_MSR); - msr_t mask = rdmsr(SMM_MASK_MSR); - int tvalid = !!(mask.lo & SMM_TSEG_VALID); - - if (hwcr.lo & SMM_LOCK) { - if (!tvalid) /* not valid but locked means still accessible */ - return; - - printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); - return; - } - - mask.lo &= ~SMM_TSEG_VALID; - wrmsr(SMM_MASK_MSR, mask); -} - void smm_region(uintptr_t *start, size_t *size) { static int once; -- To view, visit https://review.coreboot.org/c/coreboot/+/50466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e Gerrit-Change-Number: 50466 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handler
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50465 ) Change subject: soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handler ...................................................................... soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handler Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4140fbf93e84a2620ffb88e5c65df17b23135553 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50465 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/smihandler.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c index b941293..46164e4 100644 --- a/src/soc/amd/cezanne/smihandler.c +++ b/src/soc/amd/cezanne/smihandler.c @@ -1,6 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <amdblocks/smm.h> +#include <cpu/x86/smm.h> + +int southbridge_io_trap_handler(int smif) +{ + return 0; +} void *get_smi_source_handler(int source) { -- To view, visit https://review.coreboot.org/c/coreboot/+/50465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4140fbf93e84a2620ffb88e5c65df17b23135553 Gerrit-Change-Number: 50465 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd: include cpu/x86/smm directory in common SMM Makefile
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50464 ) Change subject: soc/amd: include cpu/x86/smm directory in common SMM Makefile ...................................................................... soc/amd: include cpu/x86/smm directory in common SMM Makefile Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id6be7aa7f295e61f873bfae1fca42260d3b0db78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50464 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/block/cpu/smm/Makefile.inc M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc 4 files changed, 2 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 3501282..e6bccc3 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm # Beware that all-y also adds the compilation unit to verstage on PSP all-y += config.c diff --git a/src/soc/amd/common/block/cpu/smm/Makefile.inc b/src/soc/amd/common/block/cpu/smm/Makefile.inc index c881522..df54d93 100644 --- a/src/soc/amd/common/block/cpu/smm/Makefile.inc +++ b/src/soc/amd/common/block/cpu/smm/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMM),y) +subdirs-y += ../../../../../../cpu/x86/smm + ramstage-y += smm_relocate.c smm-y += smi_handler.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index ddab522..d81eddc 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae -subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage # Beware that all-y also adds the compilation unit to verstage on PSP diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index f711c3a..856f6e6 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae -subdirs-y += ../../../cpu/x86/smm bootblock-y += uart.c bootblock-y += BiosCallOuts.c -- To view, visit https://review.coreboot.org/c/coreboot/+/50464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6be7aa7f295e61f873bfae1fca42260d3b0db78 Gerrit-Change-Number: 50464 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd: move southbridge_smi_handler to common code
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50463 ) Change subject: soc/amd: move southbridge_smi_handler to common code ...................................................................... soc/amd: move southbridge_smi_handler to common code Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I650498321736eee3d33af51216eda1b650f11744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50463 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/smihandler.c M src/soc/amd/common/block/cpu/smm/Makefile.inc A src/soc/amd/common/block/cpu/smm/smi_handler.c M src/soc/amd/common/block/include/amdblocks/smm.h M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c 6 files changed, 59 insertions(+), 90 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c index 2d9e487..b941293 100644 --- a/src/soc/amd/cezanne/smihandler.c +++ b/src/soc/amd/cezanne/smihandler.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <cpu/x86/smm.h> +#include <amdblocks/smm.h> -void southbridge_smi_handler(void) +void *get_smi_source_handler(int source) { + return NULL; } diff --git a/src/soc/amd/common/block/cpu/smm/Makefile.inc b/src/soc/amd/common/block/cpu/smm/Makefile.inc index 0639890..c881522 100644 --- a/src/soc/amd/common/block/cpu/smm/Makefile.inc +++ b/src/soc/amd/common/block/cpu/smm/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMM),y) ramstage-y += smm_relocate.c +smm-y += smi_handler.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/common/block/cpu/smm/smi_handler.c b/src/soc/amd/common/block/cpu/smm/smi_handler.c new file mode 100644 index 0000000..00c03f0 --- /dev/null +++ b/src/soc/amd/common/block/cpu/smm/smi_handler.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/acpimmio.h> +#include <amdblocks/smi.h> +#include <amdblocks/smm.h> +#include <cpu/x86/smm.h> +#include <soc/smi.h> + +static void process_smi_sources(uint32_t reg) +{ + const uint32_t status = smi_read32(reg); + int bit_zero = 32 / sizeof(uint32_t) * (reg - SMI_REG_SMISTS0); + void (*source_handler)(void); + int i; + + for (i = 0 ; i < 32 ; i++) { + if (status & (1 << i)) { + source_handler = get_smi_source_handler(i + bit_zero); + if (source_handler) + source_handler(); + } + } + + if (reg == SMI_REG_SMISTS0) + if (status & GEVENT_MASK) + /* Gevent[23:0] are assumed to be mainboard-specific */ + mainboard_smi_gpi(status & GEVENT_MASK); + + /* Clear all events in this register */ + smi_write32(reg, status); +} + +void southbridge_smi_handler(void) +{ + const uint16_t smi_src = smi_read16(SMI_REG_POINTER); + + if (smi_src & SMI_STATUS_SRC_SCI) + /* Clear events to prevent re-entering SMI if event isn't handled */ + clear_smi_sci_status(); + if (smi_src & SMI_STATUS_SRC_0) + process_smi_sources(SMI_REG_SMISTS0); + if (smi_src & SMI_STATUS_SRC_1) + process_smi_sources(SMI_REG_SMISTS1); + if (smi_src & SMI_STATUS_SRC_2) + process_smi_sources(SMI_REG_SMISTS2); + if (smi_src & SMI_STATUS_SRC_3) + process_smi_sources(SMI_REG_SMISTS3); + if (smi_src & SMI_STATUS_SRC_4) + process_smi_sources(SMI_REG_SMISTS4); +} diff --git a/src/soc/amd/common/block/include/amdblocks/smm.h b/src/soc/amd/common/block/include/amdblocks/smm.h index 0fbef42..637f034 100644 --- a/src/soc/amd/common/block/include/amdblocks/smm.h +++ b/src/soc/amd/common/block/include/amdblocks/smm.h @@ -10,3 +10,4 @@ void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); +void *get_smi_source_handler(int source); diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 626daad..928669d 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -15,6 +15,7 @@ #include <amdblocks/acpi.h> #include <amdblocks/psp.h> #include <amdblocks/smi.h> +#include <amdblocks/smm.h> #include <elog.h> #include <soc/smu.h> @@ -222,7 +223,7 @@ { .type = SMITYPE_SLP_TYP, .handler = sb_slp_typ_handler}, }; -static void *get_source_handler(int source) +void *get_smi_source_handler(int source) { int i; @@ -232,46 +233,3 @@ return NULL; } - -static void process_smi_sources(uint32_t reg) -{ - const uint32_t status = smi_read32(reg); - int bit_zero = 32 / sizeof(uint32_t) * (reg - SMI_REG_SMISTS0); - void (*source_handler)(void); - int i; - - for (i = 0 ; i < 32 ; i++) { - if (status & (1 << i)) { - source_handler = get_source_handler(i + bit_zero); - if (source_handler) - source_handler(); - } - } - - if (reg == SMI_REG_SMISTS0) - if (status & GEVENT_MASK) - /* Gevent[23:0] are assumed to be mainboard-specific */ - mainboard_smi_gpi(status & GEVENT_MASK); - - /* Clear all events in this register */ - smi_write32(reg, status); -} - -void southbridge_smi_handler(void) -{ - const uint16_t smi_src = smi_read16(SMI_REG_POINTER); - - if (smi_src & SMI_STATUS_SRC_SCI) - /* Clear events to prevent re-entering SMI if event isn't handled */ - clear_smi_sci_status(); - if (smi_src & SMI_STATUS_SRC_0) - process_smi_sources(SMI_REG_SMISTS0); - if (smi_src & SMI_STATUS_SRC_1) - process_smi_sources(SMI_REG_SMISTS1); - if (smi_src & SMI_STATUS_SRC_2) - process_smi_sources(SMI_REG_SMISTS2); - if (smi_src & SMI_STATUS_SRC_3) - process_smi_sources(SMI_REG_SMISTS3); - if (smi_src & SMI_STATUS_SRC_4) - process_smi_sources(SMI_REG_SMISTS4); -} diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index ffcbaea..0b0f5c1 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -14,6 +14,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> #include <amdblocks/smi.h> +#include <amdblocks/smm.h> #include <elog.h> /* bits in smm_io_trap */ @@ -217,7 +218,7 @@ { .type = SMITYPE_SLP_TYP, .handler = sb_slp_typ_handler}, }; -static void *get_source_handler(int source) +void *get_smi_source_handler(int source) { int i; @@ -227,46 +228,3 @@ return NULL; } - -static void process_smi_sources(uint32_t reg) -{ - const uint32_t status = smi_read32(reg); - int bit_zero = 32 / sizeof(uint32_t) * (reg - SMI_REG_SMISTS0); - void (*source_handler)(void); - int i; - - for (i = 0 ; i < 32 ; i++) { - if (status & (1 << i)) { - source_handler = get_source_handler(i + bit_zero); - if (source_handler) - source_handler(); - } - } - - if (reg == SMI_REG_SMISTS0) - if (status & GEVENT_MASK) - /* Gevent[23:0] are assumed to be mainboard-specific */ - mainboard_smi_gpi(status & GEVENT_MASK); - - /* Clear all events in this register */ - smi_write32(reg, status); -} - -void southbridge_smi_handler(void) -{ - const uint16_t smi_src = smi_read16(SMI_REG_POINTER); - - if (smi_src & SMI_STATUS_SRC_SCI) - /* Clear events to prevent re-entering SMI if event isn't handled */ - clear_smi_sci_status(); - if (smi_src & SMI_STATUS_SRC_0) - process_smi_sources(SMI_REG_SMISTS0); - if (smi_src & SMI_STATUS_SRC_1) - process_smi_sources(SMI_REG_SMISTS1); - if (smi_src & SMI_STATUS_SRC_2) - process_smi_sources(SMI_REG_SMISTS2); - if (smi_src & SMI_STATUS_SRC_3) - process_smi_sources(SMI_REG_SMISTS3); - if (smi_src & SMI_STATUS_SRC_4) - process_smi_sources(SMI_REG_SMISTS4); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/50463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I650498321736eee3d33af51216eda1b650f11744 Gerrit-Change-Number: 50463 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: [UNTESTED] soc/amd: move fch_enable_hpet_decode call to common code
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50514 ) Change subject: [UNTESTED] soc/amd: move fch_enable_hpet_decode call to common code ...................................................................... [UNTESTED] soc/amd: move fch_enable_hpet_decode call to common code Change-Id: I1299f0e8a9853b0ed0f2f4279d41a94092867a5a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/fch.c M src/soc/amd/common/block/smbus/sm.c M src/soc/amd/picasso/fch.c M src/soc/amd/stoneyridge/southbridge.c 4 files changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/50514/1 diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 8a9b379..3e2eade 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -52,8 +52,6 @@ void fch_init(void *chip_info) { fch_init_acpi_ports(); - - fch_enable_hpet_decode(); } void fch_final(void *chip_info) diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index 0b219e0..8559abf 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -13,6 +13,7 @@ { fch_enable_ioapic_decode(); setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); + fch_enable_hpet_decode(); } static u32 get_sm_mmio(struct device *dev) diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 6dcb68e..5d62e8e 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -235,8 +235,6 @@ sb_clk_output_48Mhz(); sb_rfmux_config_override(); - - fch_enable_hpet_decode(); } void fch_final(void *chip_info) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index e6e4ca9..161e3e8 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -401,8 +401,6 @@ void fch_init(void *chip_info) { fch_init_acpi_ports(); - - fch_enable_hpet_decode(); } static void set_sb_aoac(struct aoac_devs *aoac) -- To view, visit https://review.coreboot.org/c/coreboot/+/50514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1299f0e8a9853b0ed0f2f4279d41a94092867a5a Gerrit-Change-Number: 50514 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [UNTESTED] soc/amd/common: add and use fch_enable_ioapic_decode
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50513 ) Change subject: [UNTESTED] soc/amd/common: add and use fch_enable_ioapic_decode ...................................................................... [UNTESTED] soc/amd/common: add and use fch_enable_ioapic_decode Change-Id: Ife886451a6927965769282fc5644c2085abb9585 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/smbus/sm.c 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/50513/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index b4745b7..a294541 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -79,6 +79,11 @@ pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | HPET_FED0_EN); } +void fch_enable_ioapic_decode(void) +{ + pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | FCH_IOAPIC_EN); +} + /* PM registers are accessed a byte at a time via CD6/CD7 */ uint8_t pm_io_read8(uint8_t reg) { diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 30184a5..06ab6d9 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -18,6 +18,7 @@ #define SMBUS_ASF_IO_BASE_SHIFT 8 #define SMBUS_ASF_IO_BASE_MASK (0xff << SMBUS_ASF_IO_BASE_SHIFT) #define HPET_FED0_EN (1 << 6) +#define FCH_IOAPIC_EN (1 << 5) #define SMBUS_ASF_IO_EN (1 << 4) #define CF9_IO_EN (1 << 1) #define LEGACY_IO_EN (1 << 0) @@ -77,6 +78,7 @@ void fch_enable_legacy_io(void); void fch_io_enable_legacy_io(void); void fch_enable_hpet_decode(void); +void fch_enable_ioapic_decode(void); /* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index 1ec2730..0b219e0 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -11,6 +11,7 @@ static void sm_init(struct device *dev) { + fch_enable_ioapic_decode(); setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); } -- To view, visit https://review.coreboot.org/c/coreboot/+/50513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife886451a6927965769282fc5644c2085abb9585 Gerrit-Change-Number: 50513 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/cezanne: select soc-specific ACPI functionality
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50487 ) Change subject: soc/amd/cezanne: select soc-specific ACPI functionality ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50487/comment/eb3909e7_37498b37 PS2, Line 7: APCI > nit: ACPI Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Gerrit-Change-Number: 50487 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 01:51:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/cezanne: select soc-specific ACPI functionality
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50487 to look at the new patch set (#3). Change subject: soc/amd/cezanne: select soc-specific ACPI functionality ...................................................................... soc/amd/cezanne: select soc-specific ACPI functionality This doesn't select HAVE_ACPI_TABLES, so no ACPI tables will be generated for now. There's also no globalnvs.asl that corresponds to nvs.h yet. Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/include/soc/nvs.h M src/soc/amd/cezanne/include/soc/southbridge.h 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/50487/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Gerrit-Change-Number: 50487 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: [UNTESTED] soc/amd: add and use fch_enable_hpet_decode
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50512 ) Change subject: [UNTESTED] soc/amd: add and use fch_enable_hpet_decode ...................................................................... [UNTESTED] soc/amd: add and use fch_enable_hpet_decode On Picasso we missed setting this bit. Stoneyridge and Cezanne have the HPET decode enable bit in the same position in the same register. In the ACPI table entry written by southbridge_write_acpi_tables the HPET entry gets added, so we need to enable the decode. Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/fch.c M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/picasso/fch.c M src/soc/amd/stoneyridge/southbridge.c 5 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/50512/1 diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 3e2eade..8a9b379 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -52,6 +52,8 @@ void fch_init(void *chip_info) { fch_init_acpi_ports(); + + fch_enable_hpet_decode(); } void fch_final(void *chip_info) diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 1cacd44..b4745b7 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -74,6 +74,11 @@ pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN); } +void fch_enable_hpet_decode(void) +{ + pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | HPET_FED0_EN); +} + /* PM registers are accessed a byte at a time via CD6/CD7 */ uint8_t pm_io_read8(uint8_t reg) { diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 4b80a28..30184a5 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -17,6 +17,7 @@ #define PM_DECODE_EN 0x00 #define SMBUS_ASF_IO_BASE_SHIFT 8 #define SMBUS_ASF_IO_BASE_MASK (0xff << SMBUS_ASF_IO_BASE_SHIFT) +#define HPET_FED0_EN (1 << 6) #define SMBUS_ASF_IO_EN (1 << 4) #define CF9_IO_EN (1 << 1) #define LEGACY_IO_EN (1 << 0) @@ -75,6 +76,7 @@ void fch_enable_cf9_io(void); void fch_enable_legacy_io(void); void fch_io_enable_legacy_io(void); +void fch_enable_hpet_decode(void); /* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 5d62e8e..6dcb68e 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -235,6 +235,8 @@ sb_clk_output_48Mhz(); sb_rfmux_config_override(); + + fch_enable_hpet_decode(); } void fch_final(void *chip_info) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 161e3e8..e6e4ca9 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -401,6 +401,8 @@ void fch_init(void *chip_info) { fch_init_acpi_ports(); + + fch_enable_hpet_decode(); } static void set_sb_aoac(struct aoac_devs *aoac) -- To view, visit https://review.coreboot.org/c/coreboot/+/50512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da Gerrit-Change-Number: 50512 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021