coreboot-gerrit February 2021

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Change in coreboot[master]: trogdor: Add fingerprint power sequencing
by Julius Werner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Julius Werner, mturney mturney. Hello Shelley Chen, build bot (Jenkins), Alexandru Stan, mturney mturney, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50504 to look at the new patch set (#2). Change subject: trogdor: Add fingerprint power sequencing ...................................................................... trogdor: Add fingerprint power sequencing Some Trogdor variants will include a fingerprint sensor, so this patch adds support for its power sequencing. There is a requirement that the fingerprint power needs to be *off* for at least 200ms, and when it is turned back on it needs to stabilize for at least 3.5ms before taking the FPMCU out of reset. We meet these timing requirements by splitting the sequence across bootblock, romstage and ramstage. On current Trogdor boards we measured <end of bootblock> to <end of romstage> at ~430ms and <end of romstage> to <start of ramstage> at 12ms, so we easily meet the required numbers this way. BRANCH=trogdor BUG=b:170284663 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea --- M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/trogdor/board.h M src/mainboard/google/trogdor/chromeos.c M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/trogdor/romstage.c 5 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/50504/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea Gerrit-Change-Number: 50504 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Alexandru Stan <amstan(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: add MP init and SMM initialization
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50505 ) Change subject: soc/amd/cezanne: add MP init and SMM initialization ...................................................................... soc/amd/cezanne: add MP init and SMM initialization Change-Id: I38d52394b5f6ffb837fa753fc9e82c0450c6aae3 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/cpu.c 2 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/50505/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 88f609b..da33754 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -21,6 +21,8 @@ select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select IOAPIC + select PARALLEL_MP + select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON @@ -42,6 +44,7 @@ select SUPPORT_CPU_UCODE_IN_CBFS select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS + select X86_AMD_INIT_SIPI config CHIPSET_DEVICETREE string diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index b199d99..cfe0f8c 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -1,14 +1,57 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/cpu.h> +#include <amdblocks/smm.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <soc/cpu.h> +#include <soc/iomap.h> +#include <soc/reset.h> + +/* MP and SMM loading initialization */ + +/* + * Do essential initialization tasks before APs can be fired up - + * + * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This + * creates the MTRR solution that the APs will use. Otherwise APs will try to + * apply the incomplete solution as the BSP is calculating it. + */ +static void pre_mp_init(void) +{ + x86_setup_mtrrs_with_detect_no_above_4gb(); + x86_mtrr_check(); +} + +static void post_mp_init(void) +{ + global_smi_enable(); + apm_control(APM_CNT_SMMINFO); +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = get_smm_info, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; void mp_init_cpus(struct bus *cpu_bus) { + /* Clear for take-off */ + if (mp_init_with_smm(cpu_bus, &mp_ops) < 0) + printk(BIOS_ERR, "MP initialization failure.\n"); + + /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ + mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + set_warm_reset_flag(); } static void zen_2_3_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/50505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38d52394b5f6ffb837fa753fc9e82c0450c6aae3 Gerrit-Change-Number: 50505 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/*: Move prmrr_core_configure
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Patrick Rudolph, Tim Wawrzynczak, Subrata Banik, Andrey Petrov. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49898 ) Change subject: soc/intel/*: Move prmrr_core_configure ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2808a3989adff493aaf4175cbeccd080efaaedf Gerrit-Change-Number: 49898 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 22:52:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/{picasso,stoneyridge}/romstage.c: Use post_codes macros
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45526 ) Change subject: soc/amd/{picasso,stoneyridge}/romstage.c: Use post_codes macros ...................................................................... soc/amd/{picasso,stoneyridge}/romstage.c: Use post_codes macros Change-Id: I51782996602a4ae17058e6ff85d4e05f751a2bfd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45526/1 diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index b967431..09fc987 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -145,7 +145,7 @@ { int s3_resume; - post_code(0x40); + post_code(POST_CONSOLE_BOOT_MSG); console_init(); post_code(0x41); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 96103ef..0940569 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -69,7 +69,7 @@ bsp_agesa_call(); if (!s3_resume) { - post_code(0x40); + post_code(POST_CONSOLE_BOOT_MSG); do_agesawrapper(AMD_INIT_POST, "amdinitpost"); post_code(0x41); @@ -102,7 +102,7 @@ wrmsr(SYSCFG_MSR, sys_cfg); } else { printk(BIOS_INFO, "S3 detected\n"); - post_code(0x60); + post_code(POST_ENABLING_CACHE); do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); post_code(0x61); -- To view, visit https://review.coreboot.org/c/coreboot/+/45526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51782996602a4ae17058e6ff85d4e05f751a2bfd Gerrit-Change-Number: 45526 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: my boards: Do not include `superio.asl` twice
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50500 ) Change subject: my boards: Do not include `superio.asl` twice ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I492d4c860a50ac98acbcb3a51fa4d47c94baade3 Gerrit-Change-Number: 50500 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 22:36:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: trogdor: Add fingerprint GPIOs
by Shelley Chen (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Julius Werner, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50504 ) Change subject: trogdor: Add fingerprint GPIOs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea Gerrit-Change-Number: 50504 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Alexandru Stan <amstan(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 22:33:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: trogdor: Add fingerprint GPIOs
by Alexandru Stan (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Shelley Chen, Julius Werner, mturney mturney. Alexandru Stan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50504 ) Change subject: trogdor: Add fingerprint GPIOs ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/50504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea Gerrit-Change-Number: 50504 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Alexandru Stan <amstan(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 22:29:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: trogdor: Add fingerprint GPIOs
by Julius Werner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Shelley Chen, Alexandru Stan, mturney mturney. Hello Shelley Chen, Alexandru Stan, mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/50504 to review the following change. Change subject: trogdor: Add fingerprint GPIOs ...................................................................... trogdor: Add fingerprint GPIOs Some Trogdor variants will include a fingerprint sensor that wants to be explicitly powered off every boot for security reasons. This patch drives the relevant GPIOs. BRANCH=trogdor BUG=b:170284663 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea --- M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/trogdor/board.h M src/mainboard/google/trogdor/chromeos.c 3 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/50504/1 diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index b3ec4b5..dd9c4a6 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -8,6 +8,11 @@ def_bool y if BOARD_GOOGLE_TROGDOR def_bool n +config TROGDOR_HAS_FINGERPRINT + bool + default y if BOARD_GOOGLE_COACHZ + default n + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index ebce3b5..4dc5010 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -3,6 +3,7 @@ #ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ #define _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ +#include <assert.h> #include <boardid.h> #include <gpio.h> #include <soc/gpio.h> @@ -20,6 +21,18 @@ (CONFIG(BOARD_GOOGLE_COACHZ) ? (board_id() == 0 ? GPIO(52) : \ GPIO(67)) : GPIO(30))) +/* Fingerprint-specific GPIOs. Only for fingerprint-enabled devices (e.g. CoachZ). */ +#if CONFIG(TROGDOR_HAS_FINGERPRINT) +#define GPIO_FPMCU_BOOT0 GPIO(10) +#define GPIO_FP_RST_L GPIO(22) +#define GPIO_EN_FP_RAILS GPIO(74) +#else +#define GPIO_FPMCU_BOOT0 dead_code_t(gpio_t) +#define GPIO_FP_RST_L dead_code_t(gpio_t) +#define GPIO_EN_FP_RAILS dead_code_t(gpio_t) +#endif + + void setup_chromeos_gpios(void); #endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ */ diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index d6b1836..2136da3 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -12,9 +12,16 @@ gpio_input_pullup(GPIO_SD_CD_L); gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); gpio_output(GPIO_AMP_ENABLE, 0); + gpio_output(GPIO_BACKLIGHT_ENABLE, 0); gpio_output(GPIO_EN_PP3300_DX_EDP, 0); gpio_output(GPIO_EDP_BRIDGE_ENABLE, 0); + + if (CONFIG(TROGDOR_HAS_FINGERPRINT)) { + gpio_output(GPIO_FPMCU_BOOT0, 0); + gpio_output(GPIO_FP_RST_L, 0); + gpio_output(GPIO_EN_FP_RAILS, 0); + } } void fill_lb_gpios(struct lb_gpios *gpios) -- To view, visit https://review.coreboot.org/c/coreboot/+/50504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea Gerrit-Change-Number: 50504 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Alexandru Stan <amstan(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Alexandru Stan <amstan(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/gigabyte/ga-h61m-series: Drop useless `mainboard.asl`
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50502 ) Change subject: mb/gigabyte/ga-h61m-series: Drop useless `mainboard.asl` ...................................................................... mb/gigabyte/ga-h61m-series: Drop useless `mainboard.asl` Was copy-pasted from another board and is completely useless. Change-Id: Iedb03284b4509597cff5d39dda4f98669f2e814b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/mainboard/gigabyte/ga-h61m-series/acpi/mainboard.asl M src/mainboard/gigabyte/ga-h61m-series/dsdt.asl 2 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/50502/1 diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-h61m-series/acpi/mainboard.asl deleted file mode 100644 index f69d016..0000000 --- a/src/mainboard/gigabyte/ga-h61m-series/acpi/mainboard.asl +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId("PNP0C0C")) - } -} diff --git a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl index e950f74..05e8c1a 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl @@ -12,7 +12,6 @@ ) { #include <acpi/dsdt_top.asl> - #include "acpi/mainboard.asl" #include "acpi/platform.asl" #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/common/acpi/platform.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/50502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedb03284b4509597cff5d39dda4f98669f2e814b Gerrit-Change-Number: 50502 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard: Drop unneeded `default_brightness_levels.asl`
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Damien Zammit, Tristan Corrick, Alexander Couzens, Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50501 ) Change subject: mainboard: Drop unneeded `default_brightness_levels.asl` ...................................................................... mainboard: Drop unneeded `default_brightness_levels.asl` Desktop boards do not have any backlight control. Change-Id: Ie9f5f4d7e6ae09b3d664d53e4c03157fd4ed088e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b75pro3-m/dsdt.asl M src/mainboard/asrock/b85m_pro4/dsdt.asl M src/mainboard/asrock/g41c-gs/dsdt.asl M src/mainboard/asrock/h81m-hds/dsdt.asl M src/mainboard/asus/h61m-cs/dsdt.asl M src/mainboard/asus/maximus_iv_gene-z/dsdt.asl M src/mainboard/asus/p5qc/dsdt.asl M src/mainboard/asus/p5ql-em/dsdt.asl M src/mainboard/asus/p5qpl-am/dsdt.asl M src/mainboard/asus/p8h61-m_lx/dsdt.asl M src/mainboard/asus/p8h61-m_pro/dsdt.asl M src/mainboard/asus/p8z77-m_pro/dsdt.asl M src/mainboard/asus/p8z77-v_lx2/dsdt.asl M src/mainboard/foxconn/g41s-k/dsdt.asl M src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl M src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl M src/mainboard/gigabyte/ga-h61m-series/dsdt.asl M src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl M src/mainboard/hp/z220_sff_workstation/dsdt.asl M src/mainboard/intel/dg41wv/dsdt.asl M src/mainboard/intel/dg43gt/dsdt.asl M src/mainboard/lenovo/thinkcentre_a58/dsdt.asl M src/mainboard/msi/ms7707/dsdt.asl M src/mainboard/sapphire/pureplatinumh61/dsdt.asl M src/mainboard/supermicro/x10slm-f/dsdt.asl 25 files changed, 0 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/50501/1 diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index 0dd5e8f..255af18 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -22,7 +22,6 @@ Device (PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> #include "acpi/pci.asl" } diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl index ef9f6e4..41b73fa 100644 --- a/src/mainboard/asrock/b85m_pro4/dsdt.asl +++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl @@ -22,6 +22,5 @@ { #include <northbridge/intel/haswell/acpi/hostbridge.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/asrock/g41c-gs/dsdt.asl b/src/mainboard/asrock/g41c-gs/dsdt.asl index 12c14f7..6e545ab 100644 --- a/src/mainboard/asrock/g41c-gs/dsdt.asl +++ b/src/mainboard/asrock/g41c-gs/dsdt.asl @@ -20,7 +20,6 @@ { #include <northbridge/intel/x4x/acpi/x4x.asl> #include <southbridge/intel/i82801gx/acpi/ich7.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl index 5a56825..8d4899a 100644 --- a/src/mainboard/asrock/h81m-hds/dsdt.asl +++ b/src/mainboard/asrock/h81m-hds/dsdt.asl @@ -23,7 +23,6 @@ { #include <northbridge/intel/haswell/acpi/hostbridge.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } } diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index d1f241d..3bd9251 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -20,7 +20,6 @@ Device (\_SB.PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } diff --git a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl index b1854ca..b9fc14e 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl @@ -22,7 +22,6 @@ Device (PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl index ab44aaf..a81b48c 100644 --- a/src/mainboard/asus/p5qc/dsdt.asl +++ b/src/mainboard/asus/p5qc/dsdt.asl @@ -20,7 +20,6 @@ { #include <northbridge/intel/x4x/acpi/x4x.asl> #include <southbridge/intel/i82801jx/acpi/ich10.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/asus/p5ql-em/dsdt.asl b/src/mainboard/asus/p5ql-em/dsdt.asl index 4d49c79..4d64732 100644 --- a/src/mainboard/asus/p5ql-em/dsdt.asl +++ b/src/mainboard/asus/p5ql-em/dsdt.asl @@ -22,7 +22,6 @@ { #include <northbridge/intel/x4x/acpi/x4x.asl> #include <southbridge/intel/i82801jx/acpi/ich10.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/asus/p5qpl-am/dsdt.asl b/src/mainboard/asus/p5qpl-am/dsdt.asl index 12c14f7..6e545ab 100644 --- a/src/mainboard/asus/p5qpl-am/dsdt.asl +++ b/src/mainboard/asus/p5qpl-am/dsdt.asl @@ -20,7 +20,6 @@ { #include <northbridge/intel/x4x/acpi/x4x.asl> #include <southbridge/intel/i82801gx/acpi/ich7.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/asus/p8h61-m_lx/dsdt.asl b/src/mainboard/asus/p8h61-m_lx/dsdt.asl index b1854ca..b9fc14e 100644 --- a/src/mainboard/asus/p8h61-m_lx/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx/dsdt.asl @@ -22,7 +22,6 @@ Device (PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index c2e6dd8..9a12f1e 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -23,7 +23,6 @@ Device (PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index 37de966..19a528f 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -21,7 +21,6 @@ Device (\_SB.PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } diff --git a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl index 9a7d54b..e8e2b3a 100644 --- a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl +++ b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl @@ -21,7 +21,6 @@ Device (\_SB.PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } diff --git a/src/mainboard/foxconn/g41s-k/dsdt.asl b/src/mainboard/foxconn/g41s-k/dsdt.asl index 12c14f7..6e545ab 100644 --- a/src/mainboard/foxconn/g41s-k/dsdt.asl +++ b/src/mainboard/foxconn/g41s-k/dsdt.asl @@ -20,7 +20,6 @@ { #include <northbridge/intel/x4x/acpi/x4x.asl> #include <southbridge/intel/i82801gx/acpi/ich7.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index b70b338..fbbf7b7 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -26,7 +26,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include "acpi/pci.asl" } } diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl index 12c14f7..6e545ab 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -20,7 +20,6 @@ { #include <northbridge/intel/x4x/acpi/x4x.asl> #include <southbridge/intel/i82801gx/acpi/ich7.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl index 5ac83da..e950f74 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl @@ -24,7 +24,6 @@ Device (\_SB.PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index fd97836..6203060 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -22,7 +22,6 @@ Device (PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index fd97836..6203060 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -22,7 +22,6 @@ Device (PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } diff --git a/src/mainboard/intel/dg41wv/dsdt.asl b/src/mainboard/intel/dg41wv/dsdt.asl index 12c14f7..6e545ab 100644 --- a/src/mainboard/intel/dg41wv/dsdt.asl +++ b/src/mainboard/intel/dg41wv/dsdt.asl @@ -20,7 +20,6 @@ { #include <northbridge/intel/x4x/acpi/x4x.asl> #include <southbridge/intel/i82801gx/acpi/ich7.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/intel/dg43gt/dsdt.asl b/src/mainboard/intel/dg43gt/dsdt.asl index 242db53..1a4bb9d 100644 --- a/src/mainboard/intel/dg43gt/dsdt.asl +++ b/src/mainboard/intel/dg43gt/dsdt.asl @@ -20,7 +20,6 @@ { #include <northbridge/intel/x4x/acpi/x4x.asl> #include <southbridge/intel/i82801jx/acpi/ich10.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl index 12c14f7..6e545ab 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl @@ -20,7 +20,6 @@ { #include <northbridge/intel/x4x/acpi/x4x.asl> #include <southbridge/intel/i82801gx/acpi/ich7.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index 16440c7..59eae6d 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -21,7 +21,6 @@ Device (\_SB.PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index 0f82784..0d632ea 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -22,7 +22,6 @@ Device (PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index 1303453..dfc9919 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -22,6 +22,5 @@ { #include <northbridge/intel/haswell/acpi/hostbridge.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } -- To view, visit https://review.coreboot.org/c/coreboot/+/50501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9f5f4d7e6ae09b3d664d53e4c03157fd4ed088e Gerrit-Change-Number: 50501 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Damien Zammit Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021