coreboot-gerrit February 2021

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Change in coreboot[master]: my boards: Do not include `superio.asl` twice
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50500 ) Change subject: my boards: Do not include `superio.asl` twice ...................................................................... my boards: Do not include `superio.asl` twice The southbridge ASL already includes this file. Change-Id: I492d4c860a50ac98acbcb3a51fa4d47c94baade3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/dsdt.asl M src/mainboard/asus/p8h61-m_pro/dsdt.asl M src/mainboard/asus/p8z77-v_lx2/dsdt.asl M src/mainboard/gigabyte/ga-h61m-series/dsdt.asl 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/50500/1 diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl index 3a42604..ef9f6e4 100644 --- a/src/mainboard/asrock/b85m_pro4/dsdt.asl +++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl @@ -13,7 +13,6 @@ { #include <acpi/dsdt_top.asl> #include "acpi/platform.asl" - #include "acpi/superio.asl" #include <southbridge/intel/common/acpi/platform.asl> #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index d1f0d02..c2e6dd8 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -12,7 +12,6 @@ { #include <acpi/dsdt_top.asl> #include "acpi/platform.asl" - #include "acpi/superio.asl" #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/common/acpi/platform.asl> diff --git a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl index 0477378..9a7d54b 100644 --- a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl +++ b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl @@ -13,7 +13,6 @@ { #include <acpi/dsdt_top.asl> #include "acpi/platform.asl" - #include "acpi/superio.asl" #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/common/acpi/platform.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl index c510081..5ac83da 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl @@ -14,7 +14,6 @@ #include <acpi/dsdt_top.asl> #include "acpi/mainboard.asl" #include "acpi/platform.asl" - #include "acpi/superio.asl" #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/common/acpi/platform.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/50500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I492d4c860a50ac98acbcb3a51fa4d47c94baade3 Gerrit-Change-Number: 50500 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google: order matters in mem_parts_used.txt
by Paul Fagerburg (Code Review) 10 Feb '21

10 Feb '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50449 ) Change subject: mb/google: order matters in mem_parts_used.txt ...................................................................... mb/google: order matters in mem_parts_used.txt * Add comments to mem_parts_used.txt to point out that the order of the entries matters when assigning IDs, so always add a new part to the end of the file. * Update existing mem_parts_used.txt to add the same comment. * No updates to Zork variants, because they use an optional ID, so the order actually doesn't matter there. BUG=b:175898902 TEST=create a new variant of dalboz, trembyle, volteer, waddledee, or waddledoo, and observe that mem_parts_used.txt has the new verbiage. Signed-off-by: Paul Fagerburg <pfagerburg(a)google.com> Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50449 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt M src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt M src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt M src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt M src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt M src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt M src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt M src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt M src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt M util/mainboard/google/dalboz/template/spd/mem_parts_used.txt M util/mainboard/google/trembyle/template/spd/mem_parts_used.txt M util/mainboard/google/volteer/template/memory/mem_parts_used.txt M util/mainboard/google/waddledee/template/memory/mem_parts_used.txt M util/mainboard/google/waddledoo/template/memory/mem_parts_used.txt 14 files changed, 124 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt index 9fae769..12da315 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt @@ -1,7 +1,12 @@ # This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# # Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/lp4x -# See util/spd_tools/lp4x/README.md for more details and instructions. +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. # Part Name H9HCNNNBKMMLXR-NEE, 0 diff --git a/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt index 26c06b6..1bcd3da 100644 --- a/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt @@ -1,3 +1,14 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name MT53E512M32D2NP-046 WT:E H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt index 26c06b6..1bcd3da 100644 --- a/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt @@ -1,3 +1,14 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name MT53E512M32D2NP-046 WT:E H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt index f05a5af..8ebc665 100644 --- a/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt @@ -1,3 +1,14 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt index e916160..6828445 100644 --- a/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt @@ -1 +1,12 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt index e916160..6828445 100644 --- a/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt @@ -1 +1,12 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt index 43363e7..90fc109 100644 --- a/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt @@ -1,3 +1,14 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name MT53E512M32D2NP-046 WT:E H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A diff --git a/src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt index f51b3af..e4258b5 100644 --- a/src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt +++ b/src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt @@ -1,4 +1,11 @@ # This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# # Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. # See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt index c74fe43..76eab92 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt +++ b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt @@ -1,3 +1,14 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name MT53E512M64D4NW-046 WT:E MT53E1G64D8NW-046 WT:E H9HCNNNCRMBLPR-NEE diff --git a/util/mainboard/google/dalboz/template/spd/mem_parts_used.txt b/util/mainboard/google/dalboz/template/spd/mem_parts_used.txt index 106a705..8124e4f 100644 --- a/util/mainboard/google/dalboz/template/spd/mem_parts_used.txt +++ b/util/mainboard/google/dalboz/template/spd/mem_parts_used.txt @@ -1,9 +1,11 @@ # This is a CSV file containing a list of memory parts used by this variant. # One part per line with an optional fixed ID in column 2. # Only include a fixed ID if it is required for legacy reasons! -# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# # Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/ddr4. -# See util/spd_tools/ddr4/README.md for more details and instructions. +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. # Part Name, Fixed ID (optional) diff --git a/util/mainboard/google/trembyle/template/spd/mem_parts_used.txt b/util/mainboard/google/trembyle/template/spd/mem_parts_used.txt index 106a705..8124e4f 100644 --- a/util/mainboard/google/trembyle/template/spd/mem_parts_used.txt +++ b/util/mainboard/google/trembyle/template/spd/mem_parts_used.txt @@ -1,9 +1,11 @@ # This is a CSV file containing a list of memory parts used by this variant. # One part per line with an optional fixed ID in column 2. # Only include a fixed ID if it is required for legacy reasons! -# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# # Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/ddr4. -# See util/spd_tools/ddr4/README.md for more details and instructions. +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. # Part Name, Fixed ID (optional) diff --git a/util/mainboard/google/volteer/template/memory/mem_parts_used.txt b/util/mainboard/google/volteer/template/memory/mem_parts_used.txt index f51b3af..e4258b5 100644 --- a/util/mainboard/google/volteer/template/memory/mem_parts_used.txt +++ b/util/mainboard/google/volteer/template/memory/mem_parts_used.txt @@ -1,4 +1,11 @@ # This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# # Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. # See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name diff --git a/util/mainboard/google/waddledee/template/memory/mem_parts_used.txt b/util/mainboard/google/waddledee/template/memory/mem_parts_used.txt index 59381dc..e4258b5 100644 --- a/util/mainboard/google/waddledee/template/memory/mem_parts_used.txt +++ b/util/mainboard/google/waddledee/template/memory/mem_parts_used.txt @@ -1,6 +1,11 @@ # This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# # Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/lp4x -# See util/spd_tools/lp4x/README.md for more details and instructions. +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. # Part Name diff --git a/util/mainboard/google/waddledoo/template/memory/mem_parts_used.txt b/util/mainboard/google/waddledoo/template/memory/mem_parts_used.txt index 59381dc..e4258b5 100644 --- a/util/mainboard/google/waddledoo/template/memory/mem_parts_used.txt +++ b/util/mainboard/google/waddledoo/template/memory/mem_parts_used.txt @@ -1,6 +1,11 @@ # This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# # Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/lp4x -# See util/spd_tools/lp4x/README.md for more details and instructions. +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. # Part Name -- To view, visit https://review.coreboot.org/c/coreboot/+/50449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02 Gerrit-Change-Number: 50449 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/xeon_sp: Add PCH lockdown
by Arthur Heymans (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Marc Jones, Furquan Shaikh, Martin Roth, Jonathan Zhang, Johnny Lin, Rocky Phagura, Stefan Reinauer, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49849 ) Change subject: soc/intel/xeon_sp: Add PCH lockdown ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab97123e487f4f13f874f364a9c51723d234d4f0 Gerrit-Change-Number: 49849 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 21:53:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge: drop empty sb_enable
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50437 ) Change subject: soc/amd/stoneyridge: drop empty sb_enable ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b6e0bd5c7358e2f18f929d5b098d95acbf59a5c Gerrit-Change-Number: 50437 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 21:51:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statement
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50436 ) Change subject: soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statement ...................................................................... soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statement This also aligns Stoneyridge with Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I35bf9915e3502c22e9dd9efa80b00a1ce70f187d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50436 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/stoneyridge/chip.c 1 file changed, 12 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 91b04c5..9cae98b 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -105,15 +105,23 @@ static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) + switch (dev->path.type) { + case DEVICE_PATH_DOMAIN: dev->ops = &pci_domain_ops; - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + break; + case DEVICE_PATH_CPU_CLUSTER: dev->ops = &cpu_bus_ops; - else if (dev->path.type == DEVICE_PATH_PCI) + break; + case DEVICE_PATH_PCI: sb_enable(dev); - else if (dev->path.type == DEVICE_PATH_MMIO) + break; + case DEVICE_PATH_MMIO: if (i2c_acpi_name(dev) != NULL) dev->ops = &stoneyridge_i2c_mmio_ops; + break; + default: + break; + } } static void soc_init(void *chip_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/50436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35bf9915e3502c22e9dd9efa80b00a1ce70f187d Gerrit-Change-Number: 50436 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statement
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50436 ) Change subject: soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statement ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35bf9915e3502c22e9dd9efa80b00a1ce70f187d Gerrit-Change-Number: 50436 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 21:50:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncar
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50401 ) Change subject: soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncar ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Needs to be manually rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/50401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041 Gerrit-Change-Number: 50401 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 21:49:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_mini: move mainboard asl under variant
by Matt DeVillier (Code Review) 10 Feb '21

10 Feb '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50499 ) Change subject: mb/purism/librem_mini: move mainboard asl under variant ...................................................................... mb/purism/librem_mini: move mainboard asl under variant Upcoming librem_cnl variant(s) won't share mainboard asl. Change-Id: I9c2c43e5ae5efe161cc2135c920a1b9dee5a1317 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/dsdt.asl R src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/50499/1 diff --git a/src/mainboard/purism/librem_cnl/dsdt.asl b/src/mainboard/purism/librem_cnl/dsdt.asl index df3f726..0669e92 100644 --- a/src/mainboard/purism/librem_cnl/dsdt.asl +++ b/src/mainboard/purism/librem_cnl/dsdt.asl @@ -23,5 +23,5 @@ #include <southbridge/intel/common/acpi/sleepstates.asl> - #include "acpi/mainboard.asl" + #include <variant/acpi/variant.asl> } diff --git a/src/mainboard/purism/librem_cnl/acpi/mainboard.asl b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl similarity index 100% rename from src/mainboard/purism/librem_cnl/acpi/mainboard.asl rename to src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/50499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c2c43e5ae5efe161cc2135c920a1b9dee5a1317 Gerrit-Change-Number: 50499 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Add verstage support
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50342 ) Change subject: soc/amd/cezanne: Add verstage support ...................................................................... soc/amd/cezanne: Add verstage support Setup the config required to support verstage. The offsets are the same as picasso. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50342 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 21 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 530b4e7..10c085e 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -109,10 +109,31 @@ help The amount of coreboot-allocated heap and stack usage by the FSP. +config VERSTAGE_ADDR + hex + depends on VBOOT_SEPARATE_VERSTAGE + default 0x2140000 + help + Sets the address in DRAM where verstage should be loaded if running + as a separate stage on x86. + +config VERSTAGE_SIZE + hex + depends on VBOOT_SEPARATE_VERSTAGE + default 0x80000 + help + Sets the size of DRAM allocation for verstage in linker script if + running as a separate stage on x86. + config RAMBASE hex default 0x10000000 +config RO_REGION_ONLY + string + depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A + default "apu/amdfw" + config CPU_ADDR_BITS int default 48 -- To view, visit https://review.coreboot.org/c/coreboot/+/50342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e Gerrit-Change-Number: 50342 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Angel Pons, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49749 ) Change subject: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42 Gerrit-Change-Number: 49749 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 21:39:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021