coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd: Move southbridge_write_acpi_tables
by Raul Rangel (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50509 ) Change subject: soc/amd: Move southbridge_write_acpi_tables ...................................................................... soc/amd: Move southbridge_write_acpi_tables This is common between all the chipsets. It's also required by common/block/lpc/lpc.c. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0 --- M src/soc/amd/common/block/acpi/Makefile.inc A src/soc/amd/common/block/acpi/tables.c M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/include/soc/acpi.h 8 files changed, 20 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/50509/1 diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index c6a4725..3f5d47a 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -8,5 +8,6 @@ smm-y += acpi.c ramstage-y += pm_state.c +ramstage-y += tables.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPI diff --git a/src/soc/amd/common/block/acpi/tables.c b/src/soc/amd/common/block/acpi/tables.c new file mode 100644 index 0000000..fd1f37f --- /dev/null +++ b/src/soc/amd/common/block/acpi/tables.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <amdblocks/acpi.h> +#include <device/device.h> +#include <types.h> + +unsigned long southbridge_write_acpi_tables(const struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + return acpi_write_hpet(device, current, rsdp); +} diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index aa40706..badc77b 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -3,8 +3,9 @@ #ifndef AMD_BLOCK_ACPI_H #define AMD_BLOCK_ACPI_H -#include <types.h> +#include <acpi/acpi.h> #include <amdblocks/gpio_banks.h> +#include <types.h> /* ACPI MMIO registers 0xfed80800 */ #define MMIO_ACPI_PM1_STS 0x00 @@ -47,4 +48,7 @@ struct gpio_wake_state gpio_state; }; +unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, + struct acpi_rsdp *rsdp); + #endif /* AMD_BLOCK_ACPI_H */ diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index d68814b..0434b26 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -12,6 +12,7 @@ #include <arch/ioapic.h> #include <pc80/i8254.h> #include <pc80/i8259.h> +#include <amdblocks/acpi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/espi.h> #include <amdblocks/lpc.h> diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 2f08dce..f169844 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -390,13 +390,6 @@ acpigen_pop_len(); } -unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - return acpi_write_hpet(device, current, rsdp); -} - void soc_fill_gnvs(struct global_nvs *gnvs) { /* Set unknown wake source */ diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 5ee70b0..254e5d9 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -8,9 +8,6 @@ #include <device/device.h> #include <stdint.h> -unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long current, struct acpi_rsdp *rsdp); - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index af3bf12..e9c56bc 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -158,13 +158,6 @@ acpigen_pop_len(); } -unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - return acpi_write_hpet(device, current, rsdp); -} - void soc_fill_gnvs(struct global_nvs *gnvs) { /* Set unknown wake source */ diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 4eb7f35..f0c35c0 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -12,9 +12,6 @@ #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) #endif -unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long current, struct acpi_rsdp *rsdp); - const char *soc_acpi_name(const struct device *dev); #endif /* AMD_STONEYRIDGE_ACPI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0 Gerrit-Change-Number: 50509 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: Fix missing header in amd_pci_utils.h
by Raul Rangel (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50508 ) Change subject: soc/amd/common: Fix missing header in amd_pci_utils.h ...................................................................... soc/amd/common: Fix missing header in amd_pci_utils.h This was causing a build error because size_t wasn't defined. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia467c7d6cc0f71580d0b323cb560c444d53bd7f7 --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/50508/1 diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 46fcfbf..a14aecf 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -3,7 +3,7 @@ #ifndef AMD_BLOCK_PCI_UTIL_H #define AMD_BLOCK_PCI_UTIL_H -#include <stdint.h> +#include <types.h> #include <soc/amd_pci_int_defs.h> /* FCH index/data registers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia467c7d6cc0f71580d0b323cb560c444d53bd7f7 Gerrit-Change-Number: 50508 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: select ACPI support and make the compiler happy
by Raul Rangel (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Raul Rangel has uploaded a new patch set (#4) to the change originally created by Felix Held. ( https://review.coreboot.org/c/coreboot/+/50273 ) Change subject: soc/amd/cezanne: select ACPI support and make the compiler happy ...................................................................... soc/amd/cezanne: select ACPI support and make the compiler happy Follow up patches will add more functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132 --- A src/mainboard/amd/majolica/dsdt.asl A src/mainboard/google/guybrush/dsdt.asl M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/acpi.c 5 files changed, 82 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/50273/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132 Gerrit-Change-Number: 50273 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Add PCI IRQ Router definitions
by Raul Rangel (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50451 to look at the new patch set (#2). Change subject: soc/amd/cezanne: Add PCI IRQ Router definitions ...................................................................... soc/amd/cezanne: Add PCI IRQ Router definitions These definitions were identical to picasso. The only thing I changed was that I renamed Misc1 and Misc2 to HPET_L and HPET_H. This change still doesn't write the PCI_IRQ register for all the PCI devices. We need to refactor the picasso pci_gpp code first. TEST=Boot majolica and see FCH IRQs being programmed. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/fch.c A src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h 3 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/50451/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e Gerrit-Change-Number: 50451 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/spi: Stop using a variable-length array
by Julius Werner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Angel Pons, Jacob Garber. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50480 ) Change subject: drivers/spi: Stop using a variable-length array ...................................................................... Patch Set 1: (2 comments) File src/drivers/spi/adesto.c: https://review.coreboot.org/c/coreboot/+/50480/comment/40e4a87e_d13cf89c PS1, Line 94: DEFAULT_PAGE_SIZE_SHIFT Hiding this behind a macro here doesn't feel right to me, even if it's currently the same everywhere. The goal of this API is that it shouldn't need to be the same and there should be nothing special about the 256 byte size (and I don't think there needs to be, see below). File src/drivers/spi/spi_flash.c: https://review.coreboot.org/c/coreboot/+/50480/comment/306b1c1f_7b10ceb4 PS1, Line 95: u8 buff[4 + (1 << DEFAULT_PAGE_SIZE_SHIFT)]; Rather than explicitly tying this to any page size, why not just define a constant like MAX_FLASH_CMD_DATA_SIZE (which can be 256 if that makes most sense for us), and then every caller has to make sure it doesn't exceed that number. I think the only relevant case is spi_flash_cmd_write_page_program(), so there you could just add another `chunk_len = MIN(chunk_len, MAX_FLASH_CMD_DATA_SIZE)` to put an upper bound on the amount of data we can write in one command. -- To view, visit https://review.coreboot.org/c/coreboot/+/50480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib630bff1b496bc276616989d4506a3c96f242e26 Gerrit-Change-Number: 50480 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Comment-Date: Wed, 10 Feb 2021 23:55:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable CONFIG_CHROEMOS
by Mathew King (Code Review) 10 Feb '21

10 Feb '21

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50507 ) Change subject: mb/google/guybrush: Enable CONFIG_CHROEMOS ...................................................................... mb/google/guybrush: Enable CONFIG_CHROEMOS BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk(a)chromium.org> Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87 --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/Makefile.inc A src/mainboard/google/guybrush/chromeos.c 3 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/50507/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index fe20162..6226429 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -8,8 +8,15 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select MAINBOARD_HAS_CHROMEOS select SOC_AMD_CEZANNE + +config CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_SWITCHES + config FMDFILE string default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index 1e8a88c..47c1fd1 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -1,8 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later bootblock-y += bootblock.c +ramstage-y += chromeos.c ramstage-y += mainboard.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c new file mode 100644 index 0000000..0bbe88f --- /dev/null +++ b/src/mainboard/google/guybrush/chromeos.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/50507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87 Gerrit-Change-Number: 50507 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: trogdor: Add fingerprint power sequencing
by Alexandru Stan (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Julius Werner, mturney mturney. Alexandru Stan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50504 ) Change subject: trogdor: Add fingerprint power sequencing ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Thanks for being so accommodating with the rest of the power sequence. -- To view, visit https://review.coreboot.org/c/coreboot/+/50504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea Gerrit-Change-Number: 50504 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Alexandru Stan <amstan(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 23:30:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50454 ) Change subject: soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports ...................................................................... soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50454 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/fch.c M src/soc/amd/cezanne/include/soc/southbridge.h 2 files changed, 25 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 5fb4f0a..3e2eade 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -1,12 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> +#include <amdblocks/smi.h> #include <assert.h> +#include <cpu/x86/smm.h> #include <soc/iomap.h> +#include <soc/smi.h> #include <soc/southbridge.h> static void fch_init_acpi_ports(void) { + u32 reg; + /* We use some of these ports in SMM regardless of whether or not * ACPI tables are generated. Enable these ports indiscriminately. */ @@ -17,8 +22,22 @@ pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); if (CONFIG(HAVE_SMI_HANDLER)) { - /* TODO: add code for SMI handler case */ - dead_code(); + /* APMC - SMI Command Port */ + pm_write16(PM_ACPI_SMI_CMD, APM_CNT); + configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); + + /* SMI on SlpTyp requires sending SMI before completion + response of the I/O write. */ + reg = pm_read32(PM_PCI_CTRL); + reg |= FORCE_SLPSTATE_RETRY; + pm_write32(PM_PCI_CTRL, reg); + + /* Disable SlpTyp feature */ + reg = pm_read8(PM_RST_CTRL1); + reg &= ~SLPTYPE_CONTROL_EN; + pm_write8(PM_RST_CTRL1, reg); + + configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); } else { pm_write16(PM_ACPI_SMI_CMD, 0); } diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 9353e13..dcb5ef1 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -6,6 +6,8 @@ #include <soc/iomap.h> /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PM_PCI_CTRL 0x08 +#define FORCE_SLPSTATE_RETRY BIT(25) #define PWR_RESET_CFG 0x10 #define TOGGLE_ALL_PWR_GOOD (1 << 1) #define PM_SERIRQ_CONF 0x54 @@ -50,6 +52,8 @@ #define PM_ACPI_WAKE_AS_GEVENT BIT(27) #define PM_ACPI_NB_PME_GEVENT BIT(28) #define PM_ACPI_RTC_WAKE_EN BIT(29) +#define PM_RST_CTRL1 0xbe +#define SLPTYPE_CONTROL_EN BIT(5) #define PM_LPC_GATING 0xec #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) -- To view, visit https://review.coreboot.org/c/coreboot/+/50454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114 Gerrit-Change-Number: 50454 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/*: Update microcode as specified for MP-init
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Tim Wawrzynczak, Subrata Banik, Andrey Petrov, Nathaniel L Desimone. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49899 ) Change subject: soc/intel/*: Update microcode as specified for MP-init ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/alderlake/cpu.c: https://review.coreboot.org/c/coreboot/+/49899/comment/fc36d69c_be8f401f PS13, Line 70: PRMRR > PRMRR isn't currently configured on those platforms, so a second microcode update isn't required at all? Well, "not configured" would look different ;) src/soc/intel/tigerlake/romstage/fsp_params.c: m_cfg->PrmrrSize = get_valid_prmrr_size(); src/soc/intel/icelake/romstage/fsp_params.c: m_cfg->PrmrrSize = get_valid_prmrr_size(); src/soc/intel/alderlake/romstage/fsp_params.c: m_cfg->PrmrrSize = get_valid_prmrr_size(); However, they don't select SOC_INTEL_COMMON_BLOCK_SGX, so PrmrrSize will be zero. When any board sets enable_c6dram=1, Fsp set PrmrrSize=1MB. CpuMpPpi is used (SkipMpInit=0), FSP handles the microcode reload at "End of PEI", so coreboot doesn't have to do that. When we want to revive SkipMpInit=1, we'll need to do the reload. -- To view, visit https://review.coreboot.org/c/coreboot/+/49899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf2b009ac9dd7cd462abe0f787f27b09feb6ec5b Gerrit-Change-Number: 49899 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 23:19:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/majolica/devicetree: add CPU cluster
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50506 ) Change subject: mb/amd/majolica/devicetree: add CPU cluster ...................................................................... mb/amd/majolica/devicetree: add CPU cluster Change-Id: I8d8b7f3ea2502e4e49a1290b07d84d5bbb2924a7 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/majolica/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/50506/1 diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index a141552..2479980 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -2,6 +2,9 @@ chip soc/amd/cezanne + device cpu_cluster 0 on + device lapic 0 on end + end device domain 0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/50506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d8b7f3ea2502e4e49a1290b07d84d5bbb2924a7 Gerrit-Change-Number: 50506 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021