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Change subject: mb/google/brya/var/vell: update memory settings
......................................................................
Patch Set 12:
(1 comment)
File src/mainboard/google/brya/variants/vell/memory.c:
https://review.coreboot.org/c/coreboot/+/59334/comment/e88186b1_7d0d6a0e
PS12, Line 16: .targets = {40, 36, 35, 35, 35},
Below there is a space after/before the brackets. Please make it consistent.
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Change subject: mb/google/brya/var/vell: update overridetree
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59304/comment/24e2b1f7_92df3ca4
PS8, Line 9: schematice
1. schematics
2. If they have a version/revision, please add it.
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Change subject: soc/mediatek/mt8186: build in MT8186 ATF
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59823/comment/a3d9355e_412da5e3
PS1, Line 7: soc/mediatek/mt8186: build in MT8186 ATF
Maybe:
> Enable ARM Trusted Firmware integration
https://review.coreboot.org/c/coreboot/+/59823/comment/f6528e18_95922f72
PS1, Line 9: Enable configuration to build with MT8186 arm-trusted-firmware drivers.
How does this work? The submodule does not contain MT8186 stuff (yet?).
3rdparty/arm-trusted-firmware$ ls plat/mediatek/
common mt6795 mt8173 mt8183 mt8192 mt8195
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Change subject: soc/intel/alderlake: Add support for ADL-N PCH
......................................................................
Patch Set 7: Code-Review+1
(4 comments)
Patchset:
PS7:
Thank you! Other than a few nitpicks about cosmetics, LGTM.
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/59752/comment/5cc5d6cb_b4cb7c9f
PS7, Line 20: config SOC_INTEL_ALDERLAKE_PCH_N
: bool
: select SOC_INTEL_ALDERLAKE
: help
: Choose this option if your mainboard has a PCH-N chipset.
nit: Please move this between `SOC_INTEL_ALDERLAKE_PCH_M` and `SOC_INTEL_ALDERLAKE_PCH_P` to preserve alphabetical order (M ---> N ---> P)
https://review.coreboot.org/c/coreboot/+/59752/comment/c2add202_bcfdb56c
PS7, Line 188: default 12 if SOC_INTEL_ALDERLAKE_PCH_N
nit: Same thing about alphabetical order (M ---> N ---> P) here, and for the other defaults
https://review.coreboot.org/c/coreboot/+/59752/comment/1d9f7203_2ccac8dc
PS7, Line 208: default 6 if SOC_INTEL_ALDERLAKE_PCH_M
nit: I intentionally added a space here so that the `if SOC_INTEL_ALDERLAKE_PCH_` parts are aligned to the same column
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Change subject: Documentatiion/mb/facebook/fbg1701.md: Update memory information
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59756/comment/fbee24e3_18ea1f56
PS2, Line 7: Documentatiion
> The patch is already merged.
😭
https://review.coreboot.org/c/coreboot/+/59756/comment/e67fc356_09dd7bca
PS2, Line 9: determinition
And this should be `determin*a*tion` 😭
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Change subject: mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEM
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/facebook/fbg1701/romstage.c:
https://review.coreboot.org/c/coreboot/+/59754/comment/092eeb0b_bbf45d69
PS2, Line 30: break;
> i would prefer if you set spd_index = 0 here right before the break, so it's less implicit what this […]
Done
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Change subject: Documentation: Add warning about "private" changes on Gerrit
......................................................................
Patch Set 3:
(1 comment)
File Documentation/getting_started/gerrit_guidelines.md:
https://review.coreboot.org/c/coreboot/+/59229/comment/688b78f1_4e998aae
PS3, Line 197: Note that private
> Nit: Note, private …
`Note that ...` is also correct, and it's what I'd use here. The comma in `Note, ...` kind of "breaks the reading flow" of the sentence.
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