coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEM
by Angel Pons (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Michał Żygowski, Frans Hendriks, Arthur Heymans, Felix Held, Wim Vervoorn. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59754 ) Change subject: mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEM ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/mainboard/facebook/fbg1701/romstage.c: https://review.coreboot.org/c/coreboot/+/59754/comment/1f29972f_154417b3 PS3, Line 21: u8 spd_index; : : switch (cpld_read_pcb_version()) { : case 0: /* intentional fallthrough */ : case 1: /* intentional fallthrough */ : case 2: /* intentional fallthrough */ : case 3: /* intentional fallthrough */ : case 4: /* intentional fallthrough */ : case 5: : spd_index = 0; : break; : case 6: /* intentional fallthrough */ : case 7: : spd_index = 1; : break; : default: : spd_index = 2; : break; : } Idea: Put the switch block in a helper function: static u8 get_spd_index(void) { switch (cpld_read_pcb_version()) { case 0: /* intentional fallthrough */ case 1: /* intentional fallthrough */ case 2: /* intentional fallthrough */ case 3: /* intentional fallthrough */ case 4: /* intentional fallthrough */ case 5: return 0; case 6: /* intentional fallthrough */ case 7: return 1; default: return 2; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/59754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21b5ddc430410a1e8b3e9012d0c07d278880ff47 Gerrit-Change-Number: 59754 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 10:24:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/northbridge/amd/pi/00730F01: enable PARALLEL_MP
by Michał Kopeć (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Michał Żygowski, Michał Kopeć. Hello build bot (Jenkins), Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59808 to look at the new patch set (#3). Change subject: src/northbridge/amd/pi/00730F01: enable PARALLEL_MP ...................................................................... src/northbridge/amd/pi/00730F01: enable PARALLEL_MP Disable LEGACY_SMP_INIT to enable PARALLEL_MP. TEST=TEST=Boot on PC Engines apu3 Inspired by CB:59693 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db --- M src/cpu/amd/pi/00730F01/model_16_init.c M src/northbridge/amd/pi/00730F01/Kconfig M src/northbridge/amd/pi/00730F01/northbridge.c 3 files changed, 27 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59808/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Gerrit-Change-Number: 59808 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add support for ADL-N PCH
by Usha P (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Reka Norman, Paul Menzel, Rizwan Qureshi, Angel Pons, Subrata Banik, Krishna P Bhat D, Patrick Rudolph, Kangheui Won. Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59752 ) Change subject: soc/intel/alderlake: Add support for ADL-N PCH ...................................................................... Patch Set 8: (3 comments) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/59752/comment/6848a9c1_912b9fe5 PS7, Line 20: config SOC_INTEL_ALDERLAKE_PCH_N : bool : select SOC_INTEL_ALDERLAKE : help : Choose this option if your mainboard has a PCH-N chipset. > nit: Please move this between `SOC_INTEL_ALDERLAKE_PCH_M` and `SOC_INTEL_ALDERLAKE_PCH_P` to preserv […] Ack https://review.coreboot.org/c/coreboot/+/59752/comment/dcb9e016_85983f6e PS7, Line 188: default 12 if SOC_INTEL_ALDERLAKE_PCH_N > nit: Same thing about alphabetical order (M ---> N ---> P) here, and for the other defaults Ack https://review.coreboot.org/c/coreboot/+/59752/comment/721a1ffb_bb7ed39d PS7, Line 208: default 6 if SOC_INTEL_ALDERLAKE_PCH_M > nit: I intentionally added a space here so that the `if SOC_INTEL_ALDERLAKE_PCH_` parts are aligned […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904 Gerrit-Change-Number: 59752 Gerrit-PatchSet: 8 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 10:08:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for ADL-N PCH
by Usha P (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Reka Norman, Paul Menzel, Rizwan Qureshi, Subrata Banik, Krishna P Bhat D, Patrick Rudolph, Kangheui Won. Hello build bot (Jenkins), Reka Norman, Maulik V Vaghela, Rizwan Qureshi, Tim Wawrzynczak, Angel Pons, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Patrick Rudolph, Kangheui Won, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59752 to look at the new patch set (#8). Change subject: soc/intel/alderlake: Add support for ADL-N PCH ...................................................................... soc/intel/alderlake: Add support for ADL-N PCH Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to specify the correct amount of PCIe I/O. Document number 645550 indicates that Alder Lake-N has 12 PCH root ports and no CPU root ports. Document number 645548 indicates ADL-N has 5 clock sources and 5 clock request signals. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/include/soc/bootblock.h 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/59752/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/59752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904 Gerrit-Change-Number: 59752 Gerrit-PatchSet: 8 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add Kconfigs for all PCH types
by Usha P (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Felix Singer, Tim Wawrzynczak, Subrata Banik, Usha P, Patrick Rudolph, EricR Lai. Usha P has uploaded a new patch set (#5) to the change originally created by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/59804 ) Change subject: soc/intel/alderlake: Add Kconfigs for all PCH types ...................................................................... soc/intel/alderlake: Add Kconfigs for all PCH types The Alder Lake code currently supports the PCH-M and PCH-P types, which have some differences (so far, only the amount of PCIe I/O). Mainboards can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which PCH type they use: select the option to choose PCH-M, do not select the option to choose PCH-P. While this works, it can be confusing once more PCH types are added. Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards have to explicitly choose a PCH type. Also, use this option to restrict the PCH-P defaults for PCH-dependent settings to avoid unintended reuse of the PCH-P defaults when adding a new PCH type. To make sure only one PCH type is selected, add some preprocessor in `bootblock.h` to provoke a build-time error if this requirement is not met. Kconfig doesn't seem to have a mechanism to describe sets of mutually-exclusive bool options that allows said options to be selected (a `choice` block doesn't allow its elements to be selected). Finally, adapt the ADL boards accordingly. Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/shadowmountain/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/include/soc/bootblock.h 5 files changed, 26 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/59804/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Gerrit-Change-Number: 59804 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/vell: update gpio override
by Shon Wang (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Kevin Chiu, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Wisley Chen. Shon Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59305 ) Change subject: mb/google/brya/var/vell: update gpio override ...................................................................... Patch Set 14: (6 comments) File src/mainboard/google/brya/variants/vell/gpio.c: https://review.coreboot.org/c/coreboot/+/59305/comment/5c408a1d_5634ef8b PS13, Line 54: /* H12 : I2C7_SDA ==> UWB_SDA */ : PAD_CFG_GPI_APIC(GPP_H12, NONE, PLTRST, LEVEL, NONE), : /* H13 : I2C7_SCL ==> UWB_SCL */ : PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST, LEVEL, NONE), > This looks like an I2C bus, should these be configured as NF1 instead? Done https://review.coreboot.org/c/coreboot/+/59305/comment/1c3824cf_5a24b642 PS13, Line 59: NF1 > `NF6` Done https://review.coreboot.org/c/coreboot/+/59305/comment/0c78035c_1cecb62a PS13, Line 61: NF1 > `NF6` Done https://review.coreboot.org/c/coreboot/+/59305/comment/83f4877c_403bf8cb PS13, Line 94: /*For DB2*/ : /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ : //PAD_CFG_NF(GPP_H6, NONE, DEEP, NF2), : /* H7 : I2C1_SDL ==> PCH_I2C_TPM_SCL */ : //PAD_CFG_NF(GPP_H7, NONE, DEEP, NF2), : /* B7 : ISH_12C1_SDA ==> PCH_I2C_TCHSCR_SDA */ : //PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), : /* B8 : ISH_12C1_SCL ==> PCH_I2C_TCHSCR_SCL */ : //PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), > If these depend on FW_CONFIG, then you will have to program them separately (see anahera/fw_config. […] Done https://review.coreboot.org/c/coreboot/+/59305/comment/8f0e905f_4460d22d PS13, Line 109: /* B4 : PROC_GP3 ==> SSD_PERST_L */ : PAD_CFG_GPO(GPP_B4, 0, DEEP), > This is a duplicate, B4 is programmed near the end of this table (this is what we want) Done https://review.coreboot.org/c/coreboot/+/59305/comment/f49c3cea_cafef5bf PS13, Line 150: PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), > Sorry, Please ignore the above Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Gerrit-Change-Number: 59305 Gerrit-PatchSet: 14 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 09:52:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add Kconfig for ADL_N PCH
by Usha P (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Reka Norman, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Rizwan Qureshi, Angel Pons, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Patrick Rudolph, Kangheui Won. Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59751 ) Change subject: soc/intel/alderlake: Add Kconfig for ADL_N PCH ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > +1 and also rebase on CB:59804 Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1be10aea36db5a14ca8d7cf5c087163e44554f78 Gerrit-Change-Number: 59751 Gerrit-PatchSet: 2 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 09:52:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update gpio override
by Shon Wang (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Kevin Chiu, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Wisley Chen. Shon Wang has uploaded a new patch set (#14) to the change originally created by Kevin Chiu. ( https://review.coreboot.org/c/coreboot/+/59305 ) Change subject: mb/google/brya/var/vell: update gpio override ...................................................................... mb/google/brya/var/vell: update gpio override Configure GPIOs according to schematics Update initial gpio configuration for redrix BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- A src/mainboard/google/brya/variants/vell/Makefile.inc A src/mainboard/google/brya/variants/vell/gpio.c 2 files changed, 186 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/59305/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/59305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Gerrit-Change-Number: 59305 Gerrit-PatchSet: 14 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/prodrive/hermes: Get rid of variant structure
by Justin van Son (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Patrick Rudolph, Christian Walter, Angel Pons. Justin van Son has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59671 ) Change subject: mb/prodrive/hermes: Get rid of variant structure ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/mainboard/prodrive/hermes/board_info.txt: https://review.coreboot.org/c/coreboot/+/59671/comment/d484d1e8_53b3f315 PS1, Line 4: Board URL: TBD https://prodrive-technologies.com/products/embedded-computing-systems/mothe… -- To view, visit https://review.coreboot.org/c/coreboot/+/59671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1543f5b76975b0e7183fbb759e9bae5c34151d06 Gerrit-Change-Number: 59671 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 09:50:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for ADL-N CPU Type
by Usha P (Code Review) 02 Dec '21

02 Dec '21

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59836 ) Change subject: soc/intel/alderlake: Add support for ADL-N CPU Type ...................................................................... soc/intel/alderlake: Add support for ADL-N CPU Type This patch is intended to add Alder Lake-N case for adl_cpu_type and get_supported_lpm_mask. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/include/soc/cpu.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/59836/1 diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 94658c7..be11527 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -168,6 +168,11 @@ PCI_DEVICE_ID_INTEL_ADL_S_ID_15, }; + const uint16_t adl_n_mch_ids[] = { + PCI_DEVICE_ID_INTEL_ADL_N_ID_1, + PCI_DEVICE_ID_INTEL_ADL_N_ID_2, + }; + const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT), PCI_FUNC(SA_DEVFN_ROOT)), PCI_DEVICE_ID); @@ -187,6 +192,11 @@ return ADL_S; } + for (size_t i = 0; i < ARRAY_SIZE(adl_n_mch_ids); i++) { + if (adl_n_mch_ids[i] == mchid) + return ADL_N; + } + return ADL_UNKNOWN; } @@ -195,6 +205,7 @@ enum adl_cpu_type type = get_adl_cpu_type(); switch (type) { case ADL_M: /* fallthrough */ + case ADL_N: case ADL_P: return LPM_S0i2_0 | LPM_S0i3_0; case ADL_S: diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index 233e0c2..cd6f34f 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -22,6 +22,7 @@ enum adl_cpu_type { ADL_UNKNOWN, ADL_M, + ADL_N, ADL_P, ADL_S, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d Gerrit-Change-Number: 59836 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2021