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Change subject: soc/intel/alderlake: Add Kconfigs for all PCH types
......................................................................
Patch Set 5: Code-Review+2
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Change subject: mb/google/guybrush/dewatt: initial dewatt device config
......................................................................
Patch Set 2: Code-Review+1
(3 comments)
File src/mainboard/google/guybrush/variants/dewatt/gpio.c:
https://review.coreboot.org/c/coreboot/+/59839/comment/daf54c1d_39cdfb38
PS1, Line 18: /* EN_SPKR */
> code indent should use tabs where possible
Please fix.
https://review.coreboot.org/c/coreboot/+/59839/comment/48706554_01d2084b
PS1, Line 19: PAD_GPO(GPIO_70, HIGH),
> code indent should use tabs where possible
Please fix.
https://review.coreboot.org/c/coreboot/+/59839/comment/cdfcc479_9aa22284
PS1, Line 19: PAD_GPO(GPIO_70, HIGH),
> please, no spaces at the start of a line
Please fix.
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Change subject: mb/prodrive/hermes: Add board URL
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Patch Set 1: Code-Review+1
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Change subject: mb/google/guybrush/dewatt: initial dewatt device config
......................................................................
Removed reviewer Ren Kuo.
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Change subject: soc/intel/alderlake: Add support for ADL-N PCH
......................................................................
Patch Set 8: Code-Review+1
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Change subject: src/northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
Patch Set 4:
(3 comments)
Patchset:
PS2:
> The parallel mp code copies the BSP MTRRs to APs. […]
Done
Patchset:
PS4:
Thank you for the review!
File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/59808/comment/4c544afe_e205a2de
PS2, Line 955: /*
: * APIC ID calculation is tightly coupled with AGESA v5 code.
: * This calculation MUST match the assignment calculation done
: * in LocalApicInitializationAtEarly() function.
: * And reference GetLocalApicIdForCore()
: *
: * Apply APIC enumeration rules
: * For systems with >= 16 APICs, put the IO-APICs at 0..n and
: * put the local-APICs at m..z
: *
: * This is needed because many IO-APIC devices only have 4 bits
: * for their APIC id and therefore must reside at 0..15
: */
: if ((node_nums * core_max) + ioapic_count >= 0x10) {
: lapicid_start = (ioapic_count - 1) / core_max;
: lapicid_start = (lapicid_start + 1) * core_max;
: printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start);
: }
: u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
: printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n",
: i, j, apic_id);
:
: struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
: if (cpu)
: amd_cpu_topology(cpu, i, j);
> > The comment describes what is done typically in the large core count systems. […]
Removed
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Hello build bot (Jenkins), Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59808
to look at the new patch set (#4).
Change subject: src/northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
src/northbridge/amd/pi/00730F01: enable PARALLEL_MP
Disable LEGACY_SMP_INIT to enable PARALLEL_MP.
Also remove a large amount of LAPIC code that is now unnecessary.
TEST=Boot on PC Engines apu3
Inspired by CB:59693
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db
---
M src/cpu/amd/pi/00730F01/model_16_init.c
M src/northbridge/amd/pi/00730F01/Kconfig
M src/northbridge/amd/pi/00730F01/northbridge.c
3 files changed, 27 insertions(+), 127 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59808/4
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59839 )
Change subject: mb/google/guybrush/dewatt: initial dewatt device config
......................................................................
Patch Set 1:
(3 comments)
File src/mainboard/google/guybrush/variants/dewatt/gpio.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134822):
https://review.coreboot.org/c/coreboot/+/59839/comment/da726e2e_59371367
PS1, Line 18: /* EN_SPKR */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134822):
https://review.coreboot.org/c/coreboot/+/59839/comment/3591c28b_45924803
PS1, Line 19: PAD_GPO(GPIO_70, HIGH),
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134822):
https://review.coreboot.org/c/coreboot/+/59839/comment/1192ee6a_755f98bb
PS1, Line 19: PAD_GPO(GPIO_70, HIGH),
please, no spaces at the start of a line
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