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Michał Kopeć has uploaded a new patch set (#5) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/54754 )
Change subject: cpu/x86/mp_init.c: Fix building with no smihandler
......................................................................
cpu/x86/mp_init.c: Fix building with no smihandler
The build fails because smm_stub_size() tries to find a symbol that
won't be present.
Change-Id: I73fee3cf26c0e37cca03299c6730f7b4f1ef6685
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/x86/mp_init.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/54754/5
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Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 )
Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59808/comment/29adb720_bb000d98
PS4, Line 7: src/
> Please remove.
Done
File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/59808/comment/14ab29f6_c358d928
PS4, Line 874: sysconf_init
> Looks like this is unused inside the cpu bus scanning now. […]
It's also used in `domain_read_resources`. I'm not sure where else this can be moved
https://review.coreboot.org/c/coreboot/+/59808/comment/da9e012f_bc688857
PS4, Line 900: /* The flash is now no longer cacheable. Reset to WP for performance. */
: mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE,
: MTRR_TYPE_WRPROT);
> Any reason not to do this earlier, e.g. […]
If I do it in `pre_mp_init`, Linux complains about inconsistent MTRRs. I do it in `mp_init_cpus` because that's how other AMD platforms do it, but `post_mp_init` also works, so I'll move it there.
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Hello build bot (Jenkins), Michał Żygowski, Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59808
to look at the new patch set (#5).
Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
northbridge/amd/pi/00730F01: enable PARALLEL_MP
Disable LEGACY_SMP_INIT to enable PARALLEL_MP.
Also remove a large amount of APIC code that is now unnecessary.
TEST=Boot on PC Engines apu3
Inspired by CB:59693
Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/cpu/amd/pi/00730F01/model_16_init.c
M src/northbridge/amd/pi/00730F01/Kconfig
M src/northbridge/amd/pi/00730F01/northbridge.c
3 files changed, 31 insertions(+), 127 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59808/5
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59804 )
Change subject: soc/intel/alderlake: Add Kconfigs for all PCH types
......................................................................
soc/intel/alderlake: Add Kconfigs for all PCH types
The Alder Lake code currently supports the PCH-M and PCH-P types, which
have some differences (so far, only the amount of PCIe I/O). Mainboards
can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which
PCH type they use: select the option to choose PCH-M, do not select the
option to choose PCH-P. While this works, it can be confusing once more
PCH types are added.
Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards
have to explicitly choose a PCH type. Also, use this option to restrict
the PCH-P defaults for PCH-dependent settings to avoid unintended reuse
of the PCH-P defaults when adding a new PCH type. To make sure only one
PCH type is selected, add some preprocessor in `bootblock.h` to provoke
a build-time error if this requirement is not met. Kconfig doesn't seem
to have a mechanism to describe sets of mutually-exclusive bool options
that allows said options to be selected (a `choice` block doesn't allow
its elements to be selected). Finally, adapt the ADL boards accordingly.
Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/shadowmountain/Kconfig
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/include/soc/bootblock.h
5 files changed, 26 insertions(+), 11 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Singer: Looks good to me, approved
EricR Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index a5ca942..4b25af5 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -45,7 +45,7 @@
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2
- select SOC_INTEL_ALDERLAKE
+ select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
select SOC_INTEL_CSE_LITE_SKU
select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index 2b78515..6575685 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -14,7 +14,6 @@
select HAVE_ACPI_TABLES
select HAVE_SPD_IN_CBFS
select MAINBOARD_HAS_CHROMEOS
- select SOC_INTEL_ALDERLAKE
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
@@ -23,11 +22,13 @@
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_UART_8250IO
select MAINBOARD_USES_IFD_EC_REGION
+ select SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_INTEL_ADLRVP_P_EXT_EC
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_INTEL_PMC
select INTEL_LPSS_UART_FOR_CONSOLE
+ select SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_INTEL_ADLRVP_P_MCHP
select BOARD_INTEL_ADLRVP_COMMON
@@ -36,7 +37,7 @@
select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
select EC_GOOGLE_CHROMEEC_MEC
select INTEL_LPSS_UART_FOR_CONSOLE
- select SOC_INTEL_COMMON_BLOCK_IPU
+ select SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_INTEL_ADLRVP_M
select BOARD_INTEL_ADLRVP_COMMON
diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
index 553906a..9294857 100644
--- a/src/mainboard/intel/shadowmountain/Kconfig
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -23,7 +23,7 @@
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
select PCIEXP_HOTPLUG
- select SOC_INTEL_ALDERLAKE
+ select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_CSE_LITE_SKU
select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index e5d6d6b..2f8f3da 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -1,12 +1,21 @@
config SOC_INTEL_ALDERLAKE
bool
help
- Intel Alderlake support
+ Intel Alderlake support. Mainboards should specify the PCH
+ type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead
+ of selecting this option directly.
config SOC_INTEL_ALDERLAKE_PCH_M
bool
+ select SOC_INTEL_ALDERLAKE
help
- Choose this option if you have PCH-M chipset.
+ Choose this option if your mainboard has a PCH-M chipset.
+
+config SOC_INTEL_ALDERLAKE_PCH_P
+ bool
+ select SOC_INTEL_ALDERLAKE
+ help
+ Choose this option if your mainboard has a PCH-P chipset.
if SOC_INTEL_ALDERLAKE
@@ -169,12 +178,12 @@
config MAX_PCH_ROOT_PORTS
int
default 10 if SOC_INTEL_ALDERLAKE_PCH_M
- default 12
+ default 12 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_CPU_ROOT_PORTS
int
default 1 if SOC_INTEL_ALDERLAKE_PCH_M
- default 3
+ default 3 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_ROOT_PORTS
int
@@ -183,12 +192,12 @@
config MAX_PCIE_CLOCK_SRC
int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
- default 7
+ default 7 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_PCIE_CLOCK_REQ
int
- default 6 if SOC_INTEL_ALDERLAKE_PCH_M
- default 10
+ default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 10 if SOC_INTEL_ALDERLAKE_PCH_P
config SMM_TSEG_SIZE
hex
diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h
index 0cf334f..059568d 100644
--- a/src/soc/intel/alderlake/include/soc/bootblock.h
+++ b/src/soc/intel/alderlake/include/soc/bootblock.h
@@ -3,6 +3,11 @@
#ifndef _SOC_ALDERLAKE_BOOTBLOCK_H_
#define _SOC_ALDERLAKE_BOOTBLOCK_H_
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \
+ CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1
+#error "Please select exactly one PCH type"
+#endif
+
/* Bootblock pre console init programming */
void bootblock_pch_early_init(void);
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Change subject: mb/prodrive/hermes: Correct memory RCOMP settings
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Just wondering, does FSP apply defaults when you leave those out?
I haven't tried, but it doesn't seem to be the case. It's nearly impossible to know which values MRC has used without a log.
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Change subject: src/northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
Patch Set 4: Code-Review+1
(2 comments)
Patchset:
PS4:
Looks good!
File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/59808/comment/7d2d7ccd_857bde88
PS4, Line 874: sysconf_init
Looks like this is unused inside the cpu bus scanning now. Maybe move it where it is used, the vga resources thing.
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Change subject: cpu/x86/mp_init.c: Fix building with no smihandler
......................................................................
Patch Set 4: Code-Review+2
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Change subject: src/northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/59808/comment/9d2f4ed0_afd36032
PS4, Line 900: /* The flash is now no longer cacheable. Reset to WP for performance. */
: mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE,
: MTRR_TYPE_WRPROT);
Any reason not to do this earlier, e.g. in `pre_mp_init()`? If so, why not do this in the `post_mp_init` hook of `struct mp_ops`?
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Change subject: soc/intel/denverton_ns: Use `popcnt()` helper
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> maybe "Use the `popcnt()` helper instead of looping over the first CONFIG_MAX_CPUS bits and counting […]
Updated the commit message. Thoughts?
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