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I'd like you to reexamine a change. Please visit
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Change subject: libpayload: Add boot_device_read() function
......................................................................
libpayload: Add boot_device_read() function
This patch adds a new way of implementing flash access for libpayload.
Until now all reads had to be performed using cbfs_media, which is
obsolete. From now on all reads should be performed using
boot_device_read(). This patch also provides a fallback implementation
of this function using cbfs_media, but it will be removed in the future
together with cbfs_media API.
This patch also provides a default implementation of boot_device_read()
for x86 architecture.
Change-Id: I1babd2a8414ed9de3ca49903fcb4f036997b5ff3
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
---
A payloads/libpayload/arch/x86/boot_media.c
A payloads/libpayload/include/boot_device.h
2 files changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/59492/4
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya: Fix S0i3 regression
......................................................................
mb/google/brya: Fix S0i3 regression
Keeping the PM timer enabled will disqualify an ADL system from entering
S0i3, and will also cause an increase in power during suspend states.
The PM timer is not required for brya boards, therefore disabling it.
Fixes: 0e905801 (soc/intel: transition full control over PM Timer from
FSP to coreboot)
BUG=b:206922066
TEST=Boot gimble to OS and verify S0i3 counter incrementing after exiting
S0ix suspend states.
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1
---
M src/mainboard/google/brya/Kconfig
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/59790/4
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Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59790 )
Change subject: mb/google/brya: Fix S0i3 regression
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59790/comment/1a2a8a2b_af6b03df
PS2, Line 8:
> When entering S0ix states, when the PM timer is enabled, the system is unable to enter S0i3 (PM time […]
Ack
https://review.coreboot.org/c/coreboot/+/59790/comment/1f531f50_36d7ec3d
PS2, Line 9: ACPI PM timer needs to be disabled explicitly in CB to increment S0i3
: counter as FSP has no control to do the same since
> suggestion: […]
Done
https://review.coreboot.org/c/coreboot/+/59790/comment/6882ea1d_34390132
PS2, Line 12:
> Please add the tag: […]
Done
https://review.coreboot.org/c/coreboot/+/59790/comment/861cc319_f2f2f7c6
PS2, Line 14: TEST=Boot gimble to OS and verify S0i3 counter incrementing
> After exiting S0ix suspend state, […]
Done
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Hello Lance Zhao, build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Archana Patni, Michael Niewöhner, Ronak Kanabar,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/google/brya: Fix S0i3 regression
......................................................................
mb/google/brya: Fix S0i3 regression
Keeping the PM timer enabled will disqualify an ADL system from entering
S0i3, and will also cause an increase in power during suspend states.
The PM timer is not required for brya boards, therefore disabling it.
Fixes: 0e905801 (soc/intel: transition full control over PM Timer from
FSP to coreboot)
BUG=b:206922066
TEST=Boot gimble to OS and verify S0i3 counter incrementing after exiting
S0ix suspend states.
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1
---
M src/mainboard/google/brya/Kconfig
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/59790/3
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Change subject: soc/intel/alderlake: Add support for ADL-N PCH
......................................................................
Patch Set 8: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59752/comment/3e683fed_9220b0fb
PS8, Line 8:
: Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and
: use it to specify the correct amount of PCIe I/O.
:
: Document number 645550 indicates that Alder Lake-N has
: 12 PCH root ports and no CPU root ports.
:
: Document number 645548 indicates ADL-N has 5 clock sources
: and 5 clock request signals.
nit: reflow for 72 characters wide in commit messages
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59606 )
Change subject: payloads/U-Boot: Move to v2021.10
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
The Kconfig option has not been updated to reflect this
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 )
Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
Patch Set 5:
(1 comment)
File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/59808/comment/b3b23bc0_766e0306
PS4, Line 900: /* The flash is now no longer cacheable. Reset to WP for performance. */
: mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE,
: MTRR_TYPE_WRPROT);
> Done
All BSP MTRRs are copied to the APs. Before loading the payload this MTRR is removed only the BSP which causes MTRR inconsistency because then the APs still have that WP MTRR set. APs don't need this, as all the code gets executed in dram anyway. post_mp_init might be an option but it boils down to the same as calling it after the mp init and it's consistent with other soc code.
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