coreboot-gerrit December 2021

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Change in coreboot[master]: security/intel/txt: Fix HEAP_ACM format depending on number of ACMs i...
by Michał Żygowski (Code Review) 02 Dec '21

02 Dec '21

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59519 ) Change subject: security/intel/txt: Fix HEAP_ACM format depending on number of ACMs in CBFS ...................................................................... security/intel/txt: Fix HEAP_ACM format depending on number of ACMs in CBFS Since we may have either BIOS ACM or both BIOS and SINIT ACMs in CBFS, the size of txt_heap_acm_element will be different. We cannot always hardcode the size of ACM addresses array for two ACMs. If only the BIOS ACM was included, the BDR parsing failed in TBoot due to invalid size of HEAP_ACM element. Check if SINIT ACM is present in CBFS and push properly formatted BDR region onto the TXT heap. Use two separate txt_heap_acm_element structures with different lengths. TEST=Boot QubesOS 4.0 with TBoot 1.8.2 on Dell OptiPlex 9010 with and without SINIT ACM in CBFS and see that TBoot no longer complains on the wrong size of HEAP_ACM element Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ib0c37a66d96e1ca3fb4d3f665e3ad35c6f1c5c1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59519 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/security/intel/txt/ramstage.c M src/security/intel/txt/txt_register.h 2 files changed, 114 insertions(+), 49 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 217d50c..265f81e 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -200,82 +200,139 @@ } } -static void txt_initialize_heap(void) +static void txt_heap_fill_common_bdr(struct txt_biosdataregion *bdr) { - /* - * BIOS Data Format - * Chapter C.2 - * Intel TXT Software Development Guide (Document: 315168-015) - */ - struct { - struct txt_biosdataregion bdr; - struct txt_bios_spec_ver_element spec; - struct txt_heap_acm_element heap_acm; - struct txt_extended_data_element_header end; - } __packed data = {0}; - /* TPM2.0 requires version 6 of BDT */ - data.bdr.version = CONFIG_INTEL_TXT_BDR_VERSION; + bdr->version = CONFIG_INTEL_TXT_BDR_VERSION; - data.bdr.no_logical_procs = dev_count_cpu(); - - void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); - data.bdr.bios_sinit_size = cbfs_load(CONFIG_INTEL_TXT_CBFS_SINIT_ACM, - sinit_base, - read64((void *)TXT_SINIT_SIZE)); - - if (data.bdr.bios_sinit_size) { - printk(BIOS_INFO, "TEE-TXT: Placing SINIT ACM in memory.\n"); - if (CONFIG(INTEL_TXT_LOGGING)) - txt_dump_acm_info(sinit_base); - } else { - printk(BIOS_ERR, "TEE-TXT: Couldn't locate SINIT ACM in CBFS.\n"); - /* Clear memory */ - memset(sinit_base, 0, read64((void *)TXT_SINIT_SIZE)); - } + bdr->no_logical_procs = dev_count_cpu(); /* The following have been removed from BIOS Data Table in version 6 */ size_t policy_len; void *policy_data = cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_POLICY, &policy_len); if (policy_data) { /* Point to FIT Type 9 entry in flash */ - data.bdr.lcp_pd_base = (uintptr_t)policy_data; - data.bdr.lcp_pd_size = (uint64_t)policy_len; + bdr->lcp_pd_base = (uintptr_t)policy_data; + bdr->lcp_pd_size = (uint64_t)policy_len; cbfs_unmap(policy_data); } else { printk(BIOS_ERR, "TEE-TXT: Couldn't locate LCP PD Policy in CBFS.\n"); } - data.bdr.support_acpi_ppi = 0; - data.bdr.platform_type = 0; + bdr->support_acpi_ppi = 0; + bdr->platform_type = 0; +} +static void txt_heap_fill_bios_spec(struct txt_bios_spec_ver_element *spec) +{ /* Fill in the version of the used TXT BIOS Specification */ - data.spec.header.type = HEAP_EXTDATA_TYPE_BIOS_SPEC_VER; - data.spec.header.size = sizeof(data.spec); - data.spec.ver_major = 2; - data.spec.ver_minor = 1; - data.spec.ver_revision = 0; + spec->header.type = HEAP_EXTDATA_TYPE_BIOS_SPEC_VER; + spec->header.size = sizeof(*spec); + spec->ver_major = 2; + spec->ver_minor = 1; + spec->ver_revision = 0; +} + +static void txt_heap_push_bdr_for_two_acms(u8 **heap_struct) +{ + /* + * BIOS Data Format + * Chapter C.2 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + /* Structure format for two present ACMs */ + struct { + struct txt_biosdataregion bdr; + struct txt_bios_spec_ver_element spec; + struct txt_heap_acm_element2 heap_acm; + struct txt_extended_data_element_header end; + } __packed data = {0}; + + txt_heap_fill_common_bdr(&data.bdr); + txt_heap_fill_bios_spec(&data.spec); + + void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + data.bdr.bios_sinit_size = cbfs_load(CONFIG_INTEL_TXT_CBFS_SINIT_ACM, + sinit_base, + read64((void *)TXT_SINIT_SIZE)); /* Extended elements - ACM addresses */ data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; - data.heap_acm.header.size = sizeof(data.heap_acm); - if (data.bdr.bios_sinit_size) { - data.heap_acm.num_acms = 2; - data.heap_acm.acm_addrs[1] = (uintptr_t)sinit_base; - } else { - data.heap_acm.num_acms = 1; - } + data.heap_acm.num_acms = 2; + data.heap_acm.acm_addrs[1] = (uintptr_t)sinit_base; + + printk(BIOS_INFO, "TEE-TXT: Placing SINIT ACM in memory.\n"); + if (CONFIG(INTEL_TXT_LOGGING)) + txt_dump_acm_info(sinit_base); + data.heap_acm.acm_addrs[0] = (uintptr_t)cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, NULL); + + data.heap_acm.header.size = sizeof(data.heap_acm); + /* Extended elements - End marker */ data.end.type = HEAP_EXTDATA_TYPE_END; data.end.size = sizeof(data.end); + /* BiosData */ + push_sinit_heap(heap_struct, &data, sizeof(data)); +} + +static void txt_heap_push_bdr_for_one_acm(u8 **heap_struct) +{ + /* + * BIOS Data Format + * Chapter C.2 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + /* Structure format for one present ACM */ + struct { + struct txt_biosdataregion bdr; + struct txt_bios_spec_ver_element spec; + struct txt_heap_acm_element1 heap_acm; + struct txt_extended_data_element_header end; + } __packed data = {0}; + + txt_heap_fill_common_bdr(&data.bdr); + txt_heap_fill_bios_spec(&data.spec); + + void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + /* Clear SINIT ACM memory */ + memset(sinit_base, 0, read64((void *)TXT_SINIT_SIZE)); + + /* Extended elements - ACM addresses */ + data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; + data.heap_acm.acm_addrs[0] = + (uintptr_t)cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, NULL); + data.heap_acm.num_acms = 1; + + data.heap_acm.header.size = sizeof(data.heap_acm); + + /* Extended elements - End marker */ + data.end.type = HEAP_EXTDATA_TYPE_END; + data.end.size = sizeof(data.end); + + /* BiosData */ + push_sinit_heap(heap_struct, &data, sizeof(data)); +} + +static void txt_initialize_heap(void) +{ /* Fill TXT.HEAP.BASE with 4 subregions */ u8 *heap_struct = (void *)((uintptr_t)read64((void *)TXT_HEAP_BASE)); - /* BiosData */ - push_sinit_heap(&heap_struct, &data, sizeof(data)); + /* + * Since we may have either BIOS ACM or both BIOS and SINIT ACMs in + * CBFS, the size of txt_heap_acm_element will be different. We cannot + * always hardcode the number of ACM addresses for two ACMs. If we + * include BIOS ACM only, the BDR parsing will fail in TBoot due to + * invalid sizeof BDR. Check if SINIT ACM is present in CBFS and push + * properly formatted BDR region onto the TXT heap. + */ + if (cbfs_file_exists(CONFIG_INTEL_TXT_CBFS_SINIT_ACM)) + txt_heap_push_bdr_for_two_acms(&heap_struct); + else + txt_heap_push_bdr_for_one_acm(&heap_struct); /* OsMLEData */ /* FIXME: Does firmware need to write this? */ diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index 7971884..2137715 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -252,7 +252,15 @@ uint16_t ver_revision; }; -struct __packed txt_heap_acm_element { +/* Used when only the BIOS ACM is included in CBFS */ +struct __packed txt_heap_acm_element1 { + struct txt_extended_data_element_header header; + uint32_t num_acms; // must greater 0, smaller than 3 + uint64_t acm_addrs[1]; +}; + +/* Used when both BIOS and SINIT ACMs are included in CBFS */ +struct __packed txt_heap_acm_element2 { struct txt_extended_data_element_header header; uint32_t num_acms; // must greater 0, smaller than 3 uint64_t acm_addrs[2]; 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c37a66d96e1ca3fb4d3f665e3ad35c6f1c5c1e Gerrit-Change-Number: 59519 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT
by Michał Żygowski (Code Review) 02 Dec '21

02 Dec '21

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59523 ) Change subject: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT ...................................................................... nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT Initialize the DPR register and check if SCLEAN needs to be run. Allows to reliably boot the platform if ungraceful shutdown occured or the memory controller has been locked by TXT. TEST=Dell OptiPlex 9010 with Intel TXT enabled boots successfully after 4s power button override or power cable unplug when SENTER was executed. Successfully boot QubesOS 4.0 with TBoot v1.8.2 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I4b912f121593fa55c11813262f09be1a1055e950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59523 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/romstage.c 1 file changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index d6e7ee9..71b8e12 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -10,6 +10,9 @@ #include <device/pci_def.h> #include <device/device.h> #include <northbridge/intel/sandybridge/chip.h> +#include <security/intel/txt/txt.h> +#include <security/intel/txt/txt_platform.h> +#include <security/intel/txt/txt_register.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/pmclib.h> #include <elog.h> @@ -22,6 +25,21 @@ { } +static void configure_dpr(void) +{ + union dpr_register dpr = txt_get_chipset_dpr(); + + /* + * Just need to program the size of DPR, enable and lock it. + * The dpr.top will always point to TSEG_BASE (updated by hardware). + * We do it early because it will be needed later to calculate cbmem_top. + */ + dpr.lock = 1; + dpr.epm = 1; + dpr.size = CONFIG_INTEL_TXT_DPR_SIZE; + pci_write_config32(HOST_BRIDGE, DPR, dpr.raw); +} + static void early_pch_reset_pmcon(void) { /* Reset RTC power status */ @@ -60,6 +78,11 @@ post_code(0x39); + if (CONFIG(INTEL_TXT)) { + configure_dpr(); + intel_txt_romstage_init(); + } + perform_raminit(s3resume); post_code(0x3b); 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b912f121593fa55c11813262f09be1a1055e950 Gerrit-Change-Number: 59523 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/block/systemagent: Do more fine grained resource allocation
by build bot (Jenkins) (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59845 ) Change subject: soc/block/systemagent: Do more fine grained resource allocation ...................................................................... Patch Set 1: (3 comments) File src/soc/intel/common/block/systemagent/systemagent.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134847): https://review.coreboot.org/c/coreboot/+/59845/comment/5e304a1f_7309f6f1 PS1, Line 182: printk(BIOS_DEBUG, "%s UC memory: base=0x%lx, size=0x%lx\n", __func__, base_k, size_k); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134847): https://review.coreboot.org/c/coreboot/+/59845/comment/b13e6bae_c775cefc PS1, Line 190: printk(BIOS_DEBUG, "%s TSEG: base=0x%lx, size=0x%lx\n", __func__, base_k, size_k); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134847): https://review.coreboot.org/c/coreboot/+/59845/comment/869edb63_876a3c5f PS1, Line 198: printk(BIOS_DEBUG, "%s GSM: base=0x%lx, size=0x%lx\n", __func__, base_k, size_k); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/59845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbceeb31f15ba78c9a241869b5a34cb378096dbb Gerrit-Change-Number: 59845 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 17:38:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpi/acpigen, drivers/tpm: Move definition of set_package_element_op
by build bot (Jenkins) (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59729 ) Change subject: acpi/acpigen, drivers/tpm: Move definition of set_package_element_op ...................................................................... Patch Set 3: (1 comment) File src/include/acpi/acpigen.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134843): https://review.coreboot.org/c/coreboot/+/59729/comment/c6e7de71_8878a0db PS3, Line 530: void acpigen_set_package_element_op(const char *package_name, unsigned int element, uint8_t src_op); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/59729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fe70a1f369c97c67bbc1717e6adc7c5f4ba5839 Gerrit-Change-Number: 59729 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 17:27:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs | tspi: Join hash calculation for verification and measurement
by Raul Rangel (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Jakub Czapiga, Christian Walter, Julius Werner, Arthur Heymans. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59681 ) Change subject: cbfs | tspi: Join hash calculation for verification and measurement ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70d7066c6768195077f083c7ffdfa30d9182b2b7 Gerrit-Change-Number: 59681 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 02 Dec 2021 17:22:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/block/systemagent: Do more fine grained resource allocation
by Arthur Heymans (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59845 ) Change subject: soc/block/systemagent: Do more fine grained resource allocation ...................................................................... soc/block/systemagent: Do more fine grained resource allocation Not all top_of_ram -> TOLUD is uncacheable mmio. Change-Id: Idbceeb31f15ba78c9a241869b5a34cb378096dbb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/59845/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 63c2e14..5868a16 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -175,10 +175,29 @@ sa_get_mem_map(dev, &sa_map_values[0]); - /* top_of_ram -> TOLUD */ + /* Uncacheable memory */ base_k = top_of_ram; + size_k = sa_map_values[SA_TSEG_REG] - base_k; + if (size_k) { + printk(BIOS_DEBUG, "%s UC memory: base=0x%lx, size=0x%lx\n", __func__, base_k, size_k); + mmio_resource(dev, index++, base_k / KiB, size_k / KiB); + } + + /* TSEG */ + base_k = sa_map_values[SA_TSEG_REG]; + size_k = sa_map_values[SA_BGSM_REG] - base_k; + if (size_k) { + printk(BIOS_DEBUG, "%s TSEG: base=0x%lx, size=0x%lx\n", __func__, base_k, size_k); + reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); + } + + /* GSM */ + base_k = sa_map_values[SA_BGSM_REG]; size_k = sa_map_values[SA_TOLUD_REG] - base_k; - mmio_resource(dev, index++, base_k / KiB, size_k / KiB); + if (size_k) { + printk(BIOS_DEBUG, "%s GSM: base=0x%lx, size=0x%lx\n", __func__, base_k, size_k); + mmio_resource(dev, index++, base_k / KiB, size_k / KiB); + } /* 4GiB -> TOUUD */ base_k = 4 * (GiB / KiB); /* 4GiB */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbceeb31f15ba78c9a241869b5a34cb378096dbb Gerrit-Change-Number: 59845 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/systemagent: Remove weak functions
by Arthur Heymans (Code Review) 02 Dec '21

02 Dec '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59844 ) Change subject: soc/intel/common/systemagent: Remove weak functions ...................................................................... soc/intel/common/systemagent: Remove weak functions All socs implement this and an useful implementation is expected so remove weak definitions. Change-Id: I773311ef6f8d98441ce461343066f8b25c741fbc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 0 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/59844/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index b7c6d4f..63c2e14 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -17,37 +17,6 @@ #include <types.h> #include "systemagent_def.h" -/* SoC override function */ -__weak void soc_systemagent_init(struct device *dev) -{ - /* no-op */ -} - -__weak void soc_add_fixed_mmio_resources(struct device *dev, - int *resource_cnt) -{ - /* no-op */ -} - -__weak int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, - uint64_t *mask) -{ - /* return failure for this dummy API */ - return -1; -} - -__weak unsigned long sa_write_acpi_tables(const struct device *dev, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - return current; -} - -__weak uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) -{ - return 32768; /* 32 GiB per channel */ -} - static uint8_t sa_get_ecc_type(const uint32_t capid0_a) { return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; -- To view, visit https://review.coreboot.org/c/coreboot/+/59844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I773311ef6f8d98441ce461343066f8b25c741fbc Gerrit-Change-Number: 59844 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Enable CPPCv3
by Sridhar Siricilla (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59363 to look at the new patch set (#6). Change subject: soc/intel/alderlake: Enable CPPCv3 ...................................................................... soc/intel/alderlake: Enable CPPCv3 The patch enables CPPCv3 support for Intel Alder Lake which is based on hybrid core architecture. Dependency=OS patches TEST=Verified Nominal Frequency and Nominal Performance are getting updated for ADL-P small and big cores correctly. Signed-off-by: Sridahr Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Icaacd4a4ba953d8337f557903ed2ea9da4a60fb9 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/59363/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/59363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaacd4a4ba953d8337f557903ed2ea9da4a60fb9 Gerrit-Change-Number: 59363 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratio
by Sridhar Siricilla (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59789 to look at the new patch set (#2). Change subject: soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratio ...................................................................... soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratio The patch refectors cpu_set_p_state_to_max_non_turbo_ratio(). The fuction is updated to use cpu_get_max_non_turbo_ratio(). TEST=Build the code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If73df17faaf7b870ae311460a868d52352683c0c --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/59789/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If73df17faaf7b870ae311460a868d52352683c0c Gerrit-Change-Number: 59789 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add override skip_cse_sub_part_update() for alde...
by Krishna P Bhat D (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59826 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Add override skip_cse_sub_part_update() for alderlake ...................................................................... soc/intel/alderlake: Add override skip_cse_sub_part_update() for alderlake Check the Alderlake CPU ID to determine if cse sub-paritition update is required or not. Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/59826/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Gerrit-Change-Number: 59826 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021