coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

1 participants
5525 discussions

Change in coreboot[master]: brya: keep the same TPM I2C for 4ES variants
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: YH Lin. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59849 ) Change subject: brya: keep the same TPM I2C for 4ES variants ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59849/comment/0a32bdd0_88110e58 PS1, Line 17: missing `Signed-off-by` -- To view, visit https://review.coreboot.org/c/coreboot/+/59849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549 Gerrit-Change-Number: 59849 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 22:21:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: brya: keep the same TPM I2C for 4ES variants
by YH Lin (Code Review) 02 Dec '21

02 Dec '21

YH Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59849 ) Change subject: brya: keep the same TPM I2C for 4ES variants ...................................................................... brya: keep the same TPM I2C for 4ES variants Since 4ES variants were forked from their own original variants, use the same TPM I2C as well. BRANCH=none BUG=b:201767461 TEST=emerge-brya coreboot and check the artifacts Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549 --- M src/mainboard/google/brya/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/59849/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 271603e..0d2aab6 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -73,15 +73,20 @@ config DRIVER_TPM_I2C_BUS hex default 0x3 if BOARD_GOOGLE_BRYA0 + default 0x3 if BOARD_GOOGLE_BRYA4ES default 0x3 if BOARD_GOOGLE_BRASK default 0x3 if BOARD_GOOGLE_PRIMUS + default 0x3 if BOARD_GOOGLE_PRIMUS4ES default 0x1 if BOARD_GOOGLE_GIMBLE default 0x3 if BOARD_GOOGLE_GIMBLE4ES default 0x3 if BOARD_GOOGLE_REDRIX + default 0x3 if BOARD_GOOGLE_REDRIX4ES default 0x1 if BOARD_GOOGLE_KANO default 0x3 if BOARD_GOOGLE_TAEKO + default 0x3 if BOARD_GOOGLE_TAEKO4ES default 0x1 if BOARD_GOOGLE_FELWINTER default 0x3 if BOARD_GOOGLE_ANAHERA + default 0x3 if BOARD_GOOGLE_ANAHERA4ES default 0x3 if BOARD_GOOGLE_VELL config DRIVER_TPM_I2C_ADDR -- To view, visit https://review.coreboot.org/c/coreboot/+/59849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549 Gerrit-Change-Number: 59849 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/brya: Update camera NVM parameters
by Bernardo Perez Priego (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Selma Bensaid, Tim Wawrzynczak, Paul Menzel, Andy Yeh, kiran2.kumar(a)intel.com, ShawnX Tu. Bernardo Perez Priego has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58374 ) Change subject: mb/google/brya: Update camera NVM parameters ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58374/comment/45d21804_7959f3b8 PS8, Line 8: : Change HID name from INT3499 to PRP0001 along with size and : address width. Size decreased from 10K to 2K, address width : decreased from 14 to 8. : : BUG=b:203014972 : Test= Boot board and issue commands: : `cat /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom > ./brya_imx208_eeprom.bin` : `hexdump -C brya_imx208_eeprom.bin > brya_imx208_eeprom_dump.log` : You should see the result in brya_imx208_eeprom_dump.log to be same as module : nvm file by vendor provided or meet the Intel nvm calibration format. : (e.g. first 4 bytes be 0x01, 0x03, 0x01, 0x00) : > nit: re-flow for 72 characters wide Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 Gerrit-Change-Number: 58374 Gerrit-PatchSet: 9 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: kiran2.kumar(a)intel.com Gerrit-CC: Bernardo Salvador Perez Priego <bernardospp(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Attention: kiran2.kumar(a)intel.com Gerrit-Attention: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 21:51:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Update camera NVM parameters
by Bernardo Perez Priego (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Selma Bensaid, Paul Menzel, Bernardo Perez Priego, Andy Yeh, kiran2.kumar(a)intel.com, ShawnX Tu. Hello build bot (Jenkins), Selma Bensaid, Tim Wawrzynczak, Andy Yeh, kiran2.kumar(a)intel.com, ShawnX Tu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58374 to look at the new patch set (#9). Change subject: mb/google/brya: Update camera NVM parameters ...................................................................... mb/google/brya: Update camera NVM parameters Change HID name from INT3499 to PRP0001 along with size and address width. Size decreased from 10K to 2K, address width decreased from 14 to 8. BUG=b:203014972 Test= Boot board and issue commands: `cat /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom > ./brya_imx208_eeprom.bin` `hexdump -C brya_imx208_eeprom.bin > brya_imx208_eeprom_dump.log` You should see the result in brya_imx208_eeprom_dump.log to be same as module nvm file by vendor provided or meet the Intel nvm calibration format. (e.g. first 4 bytes be 0x01, 0x03, 0x01, 0x00) Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/58374/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/58374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 Gerrit-Change-Number: 58374 Gerrit-PatchSet: 9 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: kiran2.kumar(a)intel.com Gerrit-CC: Bernardo Salvador Perez Priego <bernardospp(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Attention: kiran2.kumar(a)intel.com Gerrit-Attention: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/cse: Add support to get CSME timestamps
by Bora Guvendik (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Selma Bensaid, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58993 ) Change subject: soc/intel/common/cse: Add support to get CSME timestamps ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58993/comment/8000b92f_4a9c4d12 PS3, Line 10: while > `during` Done File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/58993/comment/5d3c1204_f8389167 PS3, Line 126: > nit: extra line Done File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/58993/comment/1eef02df_10776fff PS3, Line 153: /* Early boot performance data */ : /* 0: CSME ROM start execution */ : /* 1: EC Boot Load Done (CSME ROM starts main execution) */ : /* 2: CSME ROM completed execution / CSME RBE started */ : /* 3: CSME got ESE Init Done indication from ESE */ : /* 4: CSME RBE start PMC patch/es loading */ : /* 5: CSME RBE completed PMC patch/es loading */ : /* 6: CSME RBE set "Boot Stall Done" indication to PMC */ : /* 7: CSME start poll for PMC PPS register */ : /* 8: PMC set PPS */ : /* 9: CSME BUP start running */ : /* 10: CSME set "Host Boot Prep Done" indication to PMC */ : /* 11: CSME starts PHYs loading */ : /* 12: CSME completed PHYs loading */ : /* 13: PMC indicated CSME that xxPWRGOOD was asserted */ : /* 14: PMC indicated CSME that SYS_PWROK was asserted */ : /* 15: PMC sent "CPU_BOOT_CONFIG" start message to CSME */ : /* 16: CSME sent "CPU_BOOT_CONFIG" done message to PMC */ : /* 17: PMC indicated CSME that xxPLTRST was de-asserted */ : /* 18: PMC indicated CSME that TCO_S0 was asserted */ : /* 19: PMC sent "Core Reset Done Ack - Sent" message to CSME */ : /* 20: ACM Active indication - ACM started its execution */ : /* 21: ACM Done indication - ACM completed execution */ : /* 22: BIOS sent DRAM Init Done message */ : /* 23: CSME sent DRAM Init Done message back to BIOS */ : /* 24: CSME completed loading TCSS */ : /* 25: CSME started loading ISH Bringup module */ : /* 26: CSME completed loading ISH Bringup module */ : /* 27: CSME started loading ISH Main module */ : /* 28: CSME completed loading Main module */ : /* 29: BIOS sent "End Of Post" message to CSME */ : /* 30: CSME sent "End Of Post" ack message back to BIOS */ : /* 31: BIOS sent "Core BIOS Done" message to CSME */ : /* 32: CSME sent "Core BIOS Done" ack message back to BIOS */ : /* 33: CSME reached Firmware Init Done */ : /* 34 - 63 Reserved */ > Should we make these an enum ? sure, done. -- To view, visit https://review.coreboot.org/c/coreboot/+/58993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6f7962c49b38d458680d51ee1cd709805f73b66 Gerrit-Change-Number: 58993 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 21:48:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/cse: Add support to get CSME timestamps
by Bora Guvendik (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Bora Guvendik, Selma Bensaid, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Selma Bensaid, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58993 to look at the new patch set (#4). Change subject: soc/intel/common/cse: Add support to get CSME timestamps ...................................................................... soc/intel/common/cse: Add support to get CSME timestamps This command retrieves a set of early boot performance timestamps CSME collected during the platform last boot flow BUG=b:182575295 TEST=Verify CSME timestamps after S3 and boot. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ic6f7962c49b38d458680d51ee1cd709805f73b66 --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 165 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/58993/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6f7962c49b38d458680d51ee1cd709805f73b66 Gerrit-Change-Number: 58993 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratio
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59789 ) Change subject: soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratio ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If73df17faaf7b870ae311460a868d52352683c0c Gerrit-Change-Number: 59789 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 21:34:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Add CPU related APIs
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Sugnan Prabhu S, Sridhar Siricilla, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59124 ) Change subject: soc/intel/common: Add CPU related APIs ...................................................................... Patch Set 7: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59124/comment/e9bbdf03_68f4ffd4 PS7, Line 13: cpu_get_cpu_typ `cpu_get_cpu_type` File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/59124/comment/ee4c34f2_3b10b6f0 PS7, Line 34: #define CPUID_PROCESSOR_FREQUENCY 0x16 : : #define CPUID_HYBRID_INFORMATION 0x1a : : /* Structured Extended Feature Flags */ : #define CPUID_STRUCT_EXTENDED_FEATURE_FLAGS 0x7 : #define HYBRID_FEATURE BIT(15) please use tabs for indentation, and also align the right sides https://review.coreboot.org/c/coreboot/+/59124/comment/9bee3698_b59494cb PS7, Line 199: cpu CPU https://review.coreboot.org/c/coreboot/+/59124/comment/aa96385a_845c17a3 PS7, Line 199: cpu CPU https://review.coreboot.org/c/coreboot/+/59124/comment/1d1a1d2f_4876538e PS7, Line 212: nit: extra space https://review.coreboot.org/c/coreboot/+/59124/comment/3c9e2b18_fa8b420a PS7, Line 220: core_type What are the possible return values? https://review.coreboot.org/c/coreboot/+/59124/comment/97aa7a5a_7d6bbd87 PS7, Line 224: cpu_get_bus_frequency What unit is this in? MHz? -- To view, visit https://review.coreboot.org/c/coreboot/+/59124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I680f43952ab4abce6e342206688ad32814970a91 Gerrit-Change-Number: 59124 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 21:32:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Update camera NVM parameters
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Selma Bensaid, Paul Menzel, Bernardo Perez Priego, Andy Yeh, kiran2.kumar(a)intel.com, ShawnX Tu. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58374 ) Change subject: mb/google/brya: Update camera NVM parameters ...................................................................... Patch Set 8: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58374/comment/c697a91e_0dd64025 PS8, Line 8: : Change HID name from INT3499 to PRP0001 along with size and : address width. Size decreased from 10K to 2K, address width : decreased from 14 to 8. : : BUG=b:203014972 : Test= Boot board and issue commands: : `cat /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom > ./brya_imx208_eeprom.bin` : `hexdump -C brya_imx208_eeprom.bin > brya_imx208_eeprom_dump.log` : You should see the result in brya_imx208_eeprom_dump.log to be same as module : nvm file by vendor provided or meet the Intel nvm calibration format. : (e.g. first 4 bytes be 0x01, 0x03, 0x01, 0x00) : nit: re-flow for 72 characters wide -- To view, visit https://review.coreboot.org/c/coreboot/+/58374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 Gerrit-Change-Number: 58374 Gerrit-PatchSet: 8 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: kiran2.kumar(a)intel.com Gerrit-CC: Bernardo Salvador Perez Priego <bernardospp(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Attention: kiran2.kumar(a)intel.com Gerrit-Attention: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 21:17:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/brask: Set PL and PsysPL
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59576 ) Change subject: mb/google/brya/var/brask: Set PL and PsysPL ...................................................................... mb/google/brya/var/brask: Set PL and PsysPL 1. Set the PL1, PL2 and PL4 according to issue b:193864533 comment#55 and Intel's doc #626774. 2. Set PsysPL2 and PsysPmax according to the conclusion in issue b:193864533 comment#23 and comment#29. BUG=b:193864533 BRANCH=none TEST=Compare the measured power from adapter with the value of 'psys' from the command 'dump_intel_rapl_consumption'. Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59576 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/brask/Makefile.inc A src/mainboard/google/brya/variants/brask/ramstage.c 2 files changed, 63 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brask/Makefile.inc b/src/mainboard/google/brya/variants/brask/Makefile.inc index d38141c..bc39984 100644 --- a/src/mainboard/google/brya/variants/brask/Makefile.inc +++ b/src/mainboard/google/brya/variants/brask/Makefile.inc @@ -4,3 +4,4 @@ romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/brask/ramstage.c b/src/mainboard/google/brya/variants/brask/ramstage.c new file mode 100644 index 0000000..f5105fe --- /dev/null +++ b/src/mainboard/google/brya/variants/brask/ramstage.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 230 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in brask, the serial shunt resistor is 0.005ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 13.52A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v = (0.005ohm x 13.52A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) + * R501/(R501 + R510) = 0.47 = 15K / (15K + 16.9K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 13.52A = 202.8W + * For Type-C 20V, the Psys_pmax should be 20v x 13.52A = 270.4W + * For a barrel jack, the Psys_pmax should be 19.5v x 13.52A = 263.6W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 270.4W. Then IMVP9.1 can calculate the current system + * power = 270.4W * 5A / 13.52A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 13520, + .bj_volts_mv = 19500 +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 Gerrit-Change-Number: 59576 Gerrit-PatchSet: 7 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2021