coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/brya/var/baseboard/brask: Add power limits functions
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58241 ) Change subject: mb/google/brya/var/baseboard/brask: Add power limits functions ...................................................................... mb/google/brya/var/baseboard/brask: Add power limits functions Copy function variant_update_power_limits from brya to set power limits. Add function variant_update_psys_power_limits and copy the algorithm from puff. Add structure system_power_limits and psys_config to define and configure the psys power limits. BUG=b:193864533 BRANCH=none TEST=Build pass Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58241 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc A src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h 3 files changed, 191 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc index 1693d2e..8a4b2ac 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc @@ -4,3 +4,4 @@ romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c new file mode 100644 index 0000000..9628b44 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <soc/pci_devs.h> + +#include <drivers/intel/dptf/chip.h> +#include <intelblocks/power_limit.h> + +WEAK_DEV_PTR(dptf_policy); + +#define SET_PSYSPL2(e, w) ((e) * (w) / 100) + +static bool get_sku_index(const struct cpu_power_limits *limits, size_t num_entries, + size_t *intel_idx, size_t *brask_idx) +{ + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + u8 tdp = get_cpu_tdp(); + size_t i = 0; + + for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) { + if (mchid == cpuid_to_adl[i].cpu_id && tdp == cpuid_to_adl[i].cpu_tdp) { + *intel_idx = cpuid_to_adl[i].limits; + break; + } + } + + if (i == ARRAY_SIZE(cpuid_to_adl)) { + printk(BIOS_ERR, "Cannot find correct intel sku index.\n"); + return false; + } + + for (i = 0; i < num_entries; i++) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { + *brask_idx = i; + break; + } + } + + if (i == num_entries) { + printk(BIOS_ERR, "Cannot find correct brask sku index.\n"); + return false; + } + + return true; +} + +void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) +{ + const struct device *policy_dev; + size_t intel_idx, brask_idx; + struct drivers_intel_dptf_config *config; + struct dptf_power_limits *settings; + config_t *conf; + struct soc_power_limits_config *soc_config; + + if (!num_entries) + return; + + policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) + return; + + if (!get_sku_index(limits, num_entries, &intel_idx, &brask_idx)) + return; + + config = policy_dev->chip_info; + settings = &config->controls.power_limits; + conf = config_of_soc(); + soc_config = &conf->power_limits_config[intel_idx]; + settings->pl1.min_power = limits[brask_idx].pl1_min_power; + settings->pl1.max_power = limits[brask_idx].pl1_max_power; + settings->pl2.min_power = limits[brask_idx].pl2_min_power; + settings->pl2.max_power = limits[brask_idx].pl2_max_power; + + if (soc_config->tdp_pl2_override != 0) { + settings->pl2.max_power = soc_config->tdp_pl2_override * 1000; + settings->pl2.min_power = settings->pl2.max_power; + } + + if (soc_config->tdp_pl4 == 0) + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[brask_idx].pl4_power, + MILLIWATTS_TO_WATTS); + + printk(BIOS_INFO, "Overriding power limits PL1(mW) (%u, %u) PL2(mW) (%u, %u) PL4 (%u)\n", + settings->pl1.min_power, + settings->pl1.max_power, + settings->pl2.min_power, + settings->pl2.max_power, + soc_config->tdp_pl4); +} + +void variant_update_psys_power_limits(const struct cpu_power_limits *limits, + const struct system_power_limits *sys_limits, + size_t num_entries, + const struct psys_config *config_psys) +{ + struct soc_power_limits_config *soc_config; + const struct device *policy_dev; + size_t intel_idx, brask_idx; + u16 volts_mv, current_ma; + enum usb_chg_type type; + u32 psyspl2, pl2; + u32 pl2_default; + config_t *conf; + u32 watts; + int rv; + + if (!num_entries) + return; + + policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) + return; + + if (!get_sku_index(limits, num_entries, &intel_idx, &brask_idx)) + return; + + conf = config_of_soc(); + soc_config = &conf->power_limits_config[intel_idx]; + soc_config->tdp_pl4 = 0; + + pl2_default = DIV_ROUND_UP(limits[brask_idx].pl2_max_power, MILLIWATTS_TO_WATTS); + rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); + + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + watts = ((u32)current_ma * volts_mv) / 1000000; + + /* set psyspl2 to 97% of adapter rating */ + psyspl2 = SET_PSYSPL2(config_psys->efficiency, watts); + + /* Limit PL2 if the adapter is with lower capability */ + pl2 = (psyspl2 > pl2_default) ? pl2_default : psyspl2; + + soc_config->tdp_pl4 = psyspl2; + } else { + /* Input type is barrel jack */ + volts_mv = config_psys->bj_volts_mv; + psyspl2 = sys_limits[brask_idx].psys_pl2_power; + pl2 = pl2_default; + } + + /* voltage unit is milliVolts and current is in milliAmps */ + soc_config->psys_pmax = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / 1000000); + conf->PsysPmax = soc_config->psys_pmax; + + soc_config->tdp_pl2_override = pl2; + soc_config->tdp_psyspl2 = psyspl2; + + printk(BIOS_INFO, "Overriding PL2 (%u) PsysPL2 (%u) Psys_Pmax (%u)\n", + soc_config->tdp_pl2_override, + soc_config->tdp_psyspl2, + soc_config->psys_pmax); +} diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index 3e0fd05..b3a10e0 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -37,8 +37,40 @@ unsigned int pl4_power; }; +struct system_power_limits { + uint16_t mchid; + u8 cpu_tdp; + /* PsysPL2 in Watts */ + unsigned int psys_pl2_power; +}; + +struct psys_config { + /* + * The efficiency of type-c chargers + * For example, 'efficiency = 97' means setting 97% of max power to account for + * cable loss and FET Rdson loss in the path from the source. + */ + unsigned int efficiency; + + /* The maximum current maps to the Psys signal */ + unsigned int psys_imax_ma; + + /* The voltage of barrel jack */ + unsigned int bj_volts_mv; +}; + /* Modify Power Limit devictree settings during ramstage */ void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries); + +/* + * Modify Power Limit and PsysPL devictree settings during ramstage. + * Note, this function must be called in front of calling variant_update_power_limits. + */ +void variant_update_psys_power_limits(const struct cpu_power_limits *limits, + const struct system_power_limits *sys_limits, + size_t num_entries, + const struct psys_config *config); + #endif /*__BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Gerrit-Change-Number: 58241 Gerrit-PatchSet: 19 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/brask: Set PL and PsysPL
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: David Wu, Hou-hsun Lee, Paul Menzel, Alan Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59576 ) Change subject: mb/google/brya/var/brask: Set PL and PsysPL ...................................................................... Patch Set 6: Code-Review+2 (2 comments) File src/mainboard/google/brya/variants/brask/ramstage.c: https://review.coreboot.org/c/coreboot/+/59576/comment/eb899ab9_dac4505b PS3, Line 13: { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 }, > this matches others already in the tree too, see https://review.coreboot. […] The idea is to sort by increasing TDP. https://review.coreboot.org/c/coreboot/+/59576/comment/ea0870ea_1c9ef060 PS3, Line 23: { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 230 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 230 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 230 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 230 }, > It's better to sort it in the same way with code here https://review.coreboot. […] Again idea is to sort by TDP & psys values, not arbitrary IDs. -- To view, visit https://review.coreboot.org/c/coreboot/+/59576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 Gerrit-Change-Number: 59576 Gerrit-PatchSet: 6 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 20:59:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/baseboard/brask: Add power limits functions
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Paul Menzel, Nick Vaccaro, Zhuohao Lee, Alan Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58241 ) Change subject: mb/google/brya/var/baseboard/brask: Add power limits functions ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Gerrit-Change-Number: 58241 Gerrit-PatchSet: 18 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 20:57:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update overridetree
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Kevin Chiu, Wisley Chen, Shon Wang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59304 ) Change subject: mb/google/brya/var/vell: update overridetree ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: I think you will need to rebase your stack on master again in order to get the new `hid` change in the devicetree for the drivers/gfx/generic chip driver 👍 -- To view, visit https://review.coreboot.org/c/coreboot/+/59304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaa910eb1c5584197907963781258035c668298e Gerrit-Change-Number: 59304 Gerrit-PatchSet: 8 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 20:55:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for ADL-N CPU Type
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Kangheui Won, Maulik V Vaghela, Reka Norman, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Usha P, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59836 ) Change subject: soc/intel/alderlake: Add support for ADL-N CPU Type ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59836/comment/2cc4a48e_a55c0dde PS1, Line 9: This patch is intended to add Alder Lake-N case : for adl_cpu_type and get_supported_lpm_mask. re-flow for 72 characters wide, please -- To view, visit https://review.coreboot.org/c/coreboot/+/59836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d Gerrit-Change-Number: 59836 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 20:54:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: Swap TPM I2C with touchscreen I2C
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Malik Hsu. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59737 ) Change subject: mb/google/brya/variants/primus: Swap TPM I2C with touchscreen I2C ...................................................................... Patch Set 8: Code-Review+1 (1 comment) Patchset: PS8: need to be rebased -- To view, visit https://review.coreboot.org/c/coreboot/+/59737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief1b156b866a9aaa2919f0e209b6439c7019e939 Gerrit-Change-Number: 59737 Gerrit-PatchSet: 8 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 20:53:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59580 ) Change subject: mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C ...................................................................... mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C DVT schematic will exchange TPM_I2C3 to TPM_I2C1, that may need swap TPM I2C with touchscreen I2C to avoid TPM I2C fall on muxed ISH I2C, need change I2C map, sch amd GPIO map. b/196293623 BUG=b:207613972 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59580 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/gimble/gpio.c M src/mainboard/google/brya/variants/gimble/overridetree.cb 3 files changed, 43 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Mark Hsieh: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 38df7aa..271603e 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -75,7 +75,8 @@ default 0x3 if BOARD_GOOGLE_BRYA0 default 0x3 if BOARD_GOOGLE_BRASK default 0x3 if BOARD_GOOGLE_PRIMUS - default 0x3 if BOARD_GOOGLE_GIMBLE + default 0x1 if BOARD_GOOGLE_GIMBLE + default 0x3 if BOARD_GOOGLE_GIMBLE4ES default 0x3 if BOARD_GOOGLE_REDRIX default 0x1 if BOARD_GOOGLE_KANO default 0x3 if BOARD_GOOGLE_TAEKO diff --git a/src/mainboard/google/brya/variants/gimble/gpio.c b/src/mainboard/google/brya/variants/gimble/gpio.c index 2ea9f90..04829e5 100644 --- a/src/mainboard/google/brya/variants/gimble/gpio.c +++ b/src/mainboard/google/brya/variants/gimble/gpio.c @@ -116,10 +116,10 @@ /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA_P2 */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL_P2 */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 8b6daf2..47e81d8 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -40,6 +40,36 @@ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio and WFC | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C2 | SAR0 | + #| I2C3 | Touchscreen | + #| | | + #| | | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -156,6 +186,13 @@ end end #I2C0 device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c3 on chip drivers/i2c/hid register "generic.hid" = ""ELAN9050"" register "generic.desc" = ""ELAN Touchscreen"" @@ -176,13 +213,6 @@ device i2c 0x15 on end end end - device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end - end - end device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/59580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7 Gerrit-Change-Number: 59580 Gerrit-PatchSet: 12 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: YH Lin, Paul Menzel, Marco Chen, Mark Hsieh, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59580 ) Change subject: mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7 Gerrit-Change-Number: 59580 Gerrit-PatchSet: 11 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Dec 2021 20:51:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Swap TPM and touchscreen I2C bus
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59799 ) Change subject: mb/google/brya/var/felwinter: Swap TPM and touchscreen I2C bus ...................................................................... mb/google/brya/var/felwinter: Swap TPM and touchscreen I2C bus Follow the latest HW schematic change. BUG=b:208556921 TEST=build pass Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ic05843487ea540b8cd9a50d5f73803905fd80d49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59799 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/felwinter/gpio.c M src/mainboard/google/brya/variants/felwinter/overridetree.cb 3 files changed, 41 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index cd6c9cc..38df7aa 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -79,7 +79,7 @@ default 0x3 if BOARD_GOOGLE_REDRIX default 0x1 if BOARD_GOOGLE_KANO default 0x3 if BOARD_GOOGLE_TAEKO - default 0x3 if BOARD_GOOGLE_FELWINTER + default 0x1 if BOARD_GOOGLE_FELWINTER default 0x3 if BOARD_GOOGLE_ANAHERA default 0x3 if BOARD_GOOGLE_VELL diff --git a/src/mainboard/google/brya/variants/felwinter/gpio.c b/src/mainboard/google/brya/variants/felwinter/gpio.c index 7022a39..4c07994 100644 --- a/src/mainboard/google/brya/variants/felwinter/gpio.c +++ b/src/mainboard/google/brya/variants/felwinter/gpio.c @@ -114,10 +114,10 @@ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_D11, 1, DEEP), /* D18 : UART1_TXD ==> SD_PE_RST_L */ diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 1f835d6..2cd5ad4 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -40,6 +40,33 @@ [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | Touchscreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -206,6 +233,13 @@ end end #I2C0 device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end #I2C1 + device ref i2c3 on chip drivers/i2c/hid register "generic.hid" = ""ELAN9050"" register "generic.desc" = ""ELAN Touchscreen"" @@ -237,14 +271,7 @@ register "key.label" = ""pen_eject"" device generic 0 on end end - end - device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end - end - end + end #I2C3 device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -254,7 +281,7 @@ register "probed" = "1" device i2c 15 on end end - end + end #I2C5 device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98360A"" -- To view, visit https://review.coreboot.org/c/coreboot/+/59799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic05843487ea540b8cd9a50d5f73803905fd80d49 Gerrit-Change-Number: 59799 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants: Add ChromeOS privacy screen HID to devicetree
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59848 ) Change subject: mb/google/brya/variants: Add ChromeOS privacy screen HID to devicetree ...................................................................... mb/google/brya/variants: Add ChromeOS privacy screen HID to devicetree All ChromeOS brya variants require the provisioned privacy screen _HID ("GOOG0010") to be exposed in the ACPI tables. BUG=b:197169245 TEST=compile (already verified on redrix) Change-Id: I5a2df43642ecc12dbb873d5665c54cc814c727c9 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/59848/1 diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index dc563a4..6d268c7 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -72,6 +72,8 @@ chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" + # Use Chrome OS privacy screen _HID + register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" register "device[0].privacy.enabled" = "1" diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index dc563a4..6d268c7 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -72,6 +72,8 @@ chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" + # Use Chrome OS privacy screen _HID + register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" register "device[0].privacy.enabled" = "1" diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 67cb7f3..9531e5e 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -87,6 +87,8 @@ chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" + # Use Chrome OS privacy screen _HID + register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" register "device[0].privacy.enabled" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/59848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a2df43642ecc12dbb873d5665c54cc814c727c9 Gerrit-Change-Number: 59848 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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