coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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5525 discussions

Change in coreboot[master]: cbfs: Remove deprecated APIs
by Julius Werner (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Christian Walter, Julius Werner, Yu-Ping Wu. Hello build bot (Jenkins), Jakub Czapiga, Christian Walter, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59682 to look at the new patch set (#4). Change subject: cbfs: Remove deprecated APIs ...................................................................... cbfs: Remove deprecated APIs This patch removes all remaining pieces of the old CBFS API, now that the last straggling use cases of it have been ported to the new one (meaning cbfs_map()/cbfs_load()/etc... see CB:39304 and CB:38421). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c --- M src/commonlib/Makefile.inc D src/commonlib/cbfs.c D src/commonlib/include/commonlib/cbfs.h M src/include/cbfs.h M src/lib/cbfs.c M src/security/tpm/tspi/crtm.h M src/security/vboot/Kconfig M tests/lib/cbfs-lookup-test.c M tests/lib/cbfs-verification-test.c 9 files changed, 5 insertions(+), 483 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/59682/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Gerrit-Change-Number: 59682 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS
by Reka Norman (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Kangheui Won, Isaac Lee, Kane Chen, chris wang, Felix Held. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59558 ) Change subject: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/zork/variants/shuboz/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59558/comment/ba823fff_38974985 PS5, Line 2: fw_config > Thanks Kane. I've added a comment to https://crrev. […] Ok, so IIUC based on your comment in https://crrev.com/c/3226182, the issue isn't with probe not enabling the device as we initially thought. I've tested that the correct device is enabled when SSFC is not set (as long as the two devices have different IDs). But rather, having two codec devices in overridetree.cb means that the codec doesn't show up in the ACPI tables for some other reason? I'll have a look at the ACPI tables myself and see if I can reproduce this. -- To view, visit https://review.coreboot.org/c/coreboot/+/59558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c78aa166010ffa4d0cacc8a11d418d5a6906749 Gerrit-Change-Number: 59558 Gerrit-PatchSet: 6 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Randy Wang <ifanw(a)google.com> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Dec 2021 22:55:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake, soc/common: Add method to determine the cpu type
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Sridhar Siricilla, Arthur Heymans, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59360 ) Change subject: soc/intel/alderlake, soc/common: Add method to determine the cpu type ...................................................................... Patch Set 6: (4 comments) Patchset: PS6: Hmm, we haven't made it very easy to get data out of MP Init, have we.... unless we feel like solving that problem here... maybe this would be better off if it is 1 whole procedure that invokes `mp_run_on_all_cpus()` instead and returns/fills an array of core types for each core in the system ? WDYT? File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/59360/comment/eacd16c2_e30cd7e3 PS6, Line 15: uint8_t `enum core_type` https://review.coreboot.org/c/coreboot/+/59360/comment/29c2bb09_ce3f2f5a PS6, Line 15: uint8_t __weak get_soc_cpu_type(void) : { : return 0; : } Should not be necessary to add this weak function, instead let's just make it mandatory for platforms that select `CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID` to implement `get_soc_cpu_type`, but first that needs to have a more well-defined return type like below. File src/soc/intel/common/block/include/intelblocks/acpi.h: https://review.coreboot.org/c/coreboot/+/59360/comment/452e71ec_45119837 PS6, Line 17: Since this can return incorrect data before MP-init, then this should have an 'INVALID' or 'UNKNOWN' or similar value as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/59360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b Gerrit-Change-Number: 59360 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 22:50:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: brya: keep the same TPM I2C for 4ES variants
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: YH Lin. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59849 ) Change subject: brya: keep the same TPM I2C for 4ES variants ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59849/comment/e43cbc95_5857f68d PS1, Line 17: > missing `Signed-off-by` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549 Gerrit-Change-Number: 59849 Gerrit-PatchSet: 2 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 22:42:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Julius Werner, Krishna P Bhat D. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59685 ) Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update ...................................................................... Patch Set 16: Code-Review+1 (2 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/59685/comment/4d4babe8_30748173 PS16, Line 805: > Why not just do rdev_mmap_full() and reuse cse_sub_part_get_source_fw_version() instead of reimpleme […] true, the mmap is free https://review.coreboot.org/c/coreboot/+/59685/comment/54de71eb_116809be PS16, Line 959: /* If SOC is not Alderlake A2, skip update */ > This is generic code, so it shouldn't reference Alderlake. […] Oops missed that one -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 16 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 22:38:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: brya: keep the same TPM I2C for 4ES variants
by YH Lin (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: YH Lin. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59849 to look at the new patch set (#2). Change subject: brya: keep the same TPM I2C for 4ES variants ...................................................................... brya: keep the same TPM I2C for 4ES variants Since 4ES variants were forked from their own original variants, use the same TPM I2C as well. BRANCH=none BUG=b:201767461 TEST=emerge-brya coreboot and check the artifacts Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549 --- M src/mainboard/google/brya/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/59849/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549 Gerrit-Change-Number: 59849 Gerrit-PatchSet: 2 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake, soc/common: Add method to determine the cpu type
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

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Change in coreboot[master]: mb/google/brya: Update camera NVM parameters
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Selma Bensaid, Paul Menzel, Bernardo Perez Priego, Andy Yeh, kiran2.kumar(a)intel.com, ShawnX Tu. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58374 ) Change subject: mb/google/brya: Update camera NVM parameters ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 Gerrit-Change-Number: 58374 Gerrit-PatchSet: 9 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: kiran2.kumar(a)intel.com Gerrit-CC: Bernardo Salvador Perez Priego <bernardospp(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Attention: kiran2.kumar(a)intel.com Gerrit-Attention: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 22:22:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
by Julius Werner (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Tim Wawrzynczak, Krishna P Bhat D. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59685 ) Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update ...................................................................... Patch Set 16: (4 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/59685/comment/1b531fde_27e58673 PS16, Line 405: : __weak bool skip_cse_sub_part_update(void) : { : return false; : } > nit; I don't think this weak function definition is still required. I think this makes sense if implementing this function is a rare edge case and most future SoCs using this feature are not expected to need it. My assumption here (without knowing the background) was that the Alderlake thing was just that the earlier stepping doesn't support this because it's the first chip with it or something, but all future SoC generations would want to use it without requiring an extra runtime check. Is that roughly the idea or am I way off? If we expect that the majority of future chips will need to override this for some reason, I agree it shouldn't be weak. https://review.coreboot.org/c/coreboot/+/59685/comment/74f42618_d047394d PS16, Line 805: Why not just do rdev_mmap_full() and reuse cse_sub_part_get_source_fw_version() instead of reimplementing everything? https://review.coreboot.org/c/coreboot/+/59685/comment/f03464a2_b9927256 PS16, Line 959: /* If SOC is not Alderlake A2, skip update */ This is generic code, so it shouldn't reference Alderlake. Just say /* SoCs can implement this if they want to decide whether to apply sub part update at runtime. */ or something. File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/59685/comment/15920da5_b6a39018 PS16, Line 343: * Returns true if cse sub-parition update is required otherwise false. This should clarify that this is a weak function and what the default behavior is if the platform doesn't implement it. -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 16 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 22:22:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: brya: keep the same TPM I2C for 4ES variants
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: YH Lin. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59849 ) Change subject: brya: keep the same TPM I2C for 4ES variants ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549 Gerrit-Change-Number: 59849 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 22:22:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021