coreboot-gerrit December 2021

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Change in coreboot[master]: lib: Fix edge case of log2_ceil()
by Yu-Ping Wu (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59834 ) Change subject: lib: Fix edge case of log2_ceil() ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Could log2(x - 1) + 1 achieve the same without casting to 64 bits? That would make this more efficie […] Done, but there's no log2_ceil() in libpayload. -- To view, visit https://review.coreboot.org/c/coreboot/+/59834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If868f793b909a6ad7fc48a7affac15e2c714fa2e Gerrit-Change-Number: 59834 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 23:52:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Fix edge case of log2_ceil()
by Yu-Ping Wu (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Yu-Ping Wu. Hello build bot (Jenkins), Jakub Czapiga, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59834 to look at the new patch set (#2). Change subject: lib: Fix edge case of log2_ceil() ...................................................................... lib: Fix edge case of log2_ceil() Current log2_ceil(x) is defined as log2(x * 2 - 1). When x is larger than (1 << 31), (x * 2 - 1) won't fit in u32, leading to incorrect result. Therefore, correct it as (log2(x - 1) + 1). Also add unit tests for inline functions in lib.h. BUG=none TEST=make tests/lib/lib-test BRANCH=none Change-Id: If868f793b909a6ad7fc48a7affac15e2c714fa2e Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/include/lib.h M tests/lib/Makefile.inc A tests/lib/lib-test.c 3 files changed, 65 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59834/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If868f793b909a6ad7fc48a7affac15e2c714fa2e Gerrit-Change-Number: 59834 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cbfs: Remove deprecated APIs
by Raul Rangel (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Christian Walter, Julius Werner, Werner Zeh, Yu-Ping Wu. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59682 ) Change subject: cbfs: Remove deprecated APIs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Gerrit-Change-Number: 59682 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 23:37:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59855 ) Change subject: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3 ...................................................................... soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3 For additional power savings during RTD3, the PMC can power-gate the ModPHY lanes that are used by the PCH PCIe root ports. Therefore, using the previous PCIe RP-type detection functions, implement ModPHY PG support for the PCH PCIe RPs. This involves: 1) Adding a mutex so only one power resource accesses the PMC registers at a time 2) OperationRegions to access the PMC's PG registers 3) Adding ModPHY PG enable sequence to _OFF 4) Adding ModPHY PG disable sequence to _ON BUG=b:197983574 TEST=50 S0ix suspend/resume cycles on brya0 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 90 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/59855/1 diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 816df05..5d79c53 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -9,6 +9,8 @@ #include <device/pci.h> #include <intelblocks/pmc.h> #include <intelblocks/pmc_ipc.h> +#include <intelblocks/pcie_rp.h> +#include <soc/iomap.h> #include "chip.h" /* @@ -42,6 +44,9 @@ #define ACPI_REG_PCI_L23_RDY_DETECT "L23R" /* L23_Rdy Detect Transition */ #define ACPI_REG_PCI_L23_SAVE_STATE "NCB7" /* Scratch bit to save L23 state */ +/* ACPI path to the mutex that protects accesses to PMC ModPhy power gating registers */ +#define RTD3_MUTEX_PATH "\\_SB.PCI0.R3MX" + /* Called from _ON to get PCIe link back to active state. */ static void pcie_rtd3_acpi_l23_exit(void) { @@ -74,12 +79,49 @@ acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_SAVE_STATE); } +/* Called from _ON to disable ModPHY power gating */ +static void pcie_rtd3_disable_modphy_pg(unsigned int pcie_rp) +{ + /* Enter the critical section */ + acpigen_emit_ext_op(ACQUIRE_OP); + acpigen_emit_namestring(RTD3_MUTEX_PATH); + acpigen_emit_word(ACPI_MUTEX_NO_TIMEOUT); + + acpigen_write_store_int_to_namestr(0, "EMPG"); + acpigen_write_delay_until_namestr_int(100, "AMPG", 0); + + /* Exit the critical section */ + acpigen_emit_ext_op(RELEASE_OP); + acpigen_emit_namestring(RTD3_MUTEX_PATH); +} + +/* Called from _OFF to enable ModPHY power gating */ +static void pcie_rtd3_enable_modphy_pg(unsigned int pcie_rp) +{ + /* Enter the critical section */ + acpigen_emit_ext_op(ACQUIRE_OP); + acpigen_emit_namestring(RTD3_MUTEX_PATH); + acpigen_emit_word(ACPI_MUTEX_NO_TIMEOUT); + + acpigen_write_store_int_to_namestr(1, "EMPG"); + acpigen_write_delay_until_namestr_int(100, "AMPG", 1); + + /* Exit the critical section */ + acpigen_emit_ext_op(RELEASE_OP); + acpigen_emit_namestring(RTD3_MUTEX_PATH); +} + static void pcie_rtd3_acpi_method_on(unsigned int pcie_rp, - const struct soc_intel_common_block_pcie_rtd3_config *config) + const struct soc_intel_common_block_pcie_rtd3_config *config, + enum pcie_rp_type rp_type) { acpigen_write_method_serialized("_ON", 0); + /* Disable modPHY power gating for PCH RPs. */ + if (rp_type == PCIE_RP_PCH) + pcie_rtd3_disable_modphy_pg(pcie_rp); + /* Assert enable GPIO to turn on device power. */ if (config->enable_gpio.pin_count) { acpigen_enable_tx_gpio(&config->enable_gpio); @@ -98,7 +140,7 @@ acpigen_write_sleep(config->reset_delay_ms); } - /* Trigger L23 ready exit flow unless disabld by config. */ + /* Trigger L23 ready exit flow unless disabled by config. */ if (!config->disable_l23) pcie_rtd3_acpi_l23_exit(); @@ -107,7 +149,8 @@ static void pcie_rtd3_acpi_method_off(int pcie_rp, - const struct soc_intel_common_block_pcie_rtd3_config *config) + const struct soc_intel_common_block_pcie_rtd3_config *config, + enum pcie_rp_type rp_type) { acpigen_write_method_serialized("_OFF", 0); @@ -122,6 +165,10 @@ acpigen_write_sleep(config->reset_off_delay_ms); } + /* Enable modPHY power gating for PCH RPs */ + if (rp_type == PCIE_RP_PCH) + pcie_rtd3_enable_modphy_pg(pcie_rp); + /* Disable SRCCLK for this root port if pin is defined. */ if (config->srcclk_pin >= 0) pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, false); @@ -165,8 +212,31 @@ acpigen_pop_len(); /* Method */ } +static void write_modphy_opregion(unsigned int pcie_rp) +{ + /* The register containing the Power Gate enable sequence bits is at + PCH_PWRM_BASE + 0x10D0, and the bits to check for sequence completion are at + PCH_PWRM_BASE + 0x10D4. */ + const struct opregion opregion = OPREGION("PMCP", SYSTEMMEMORY, + PCH_PWRM_BASE_ADDRESS + 0x1000, 0xff); + const struct fieldlist fieldlist[] = { + FIELDLIST_OFFSET(0xD0), + FIELDLIST_RESERVED(pcie_rp), + FIELDLIST_NAMESTR("EMPG", 1), /* Enable ModPHY Power Gate */ + FIELDLIST_OFFSET(0xD4), + FIELDLIST_RESERVED(pcie_rp), + FIELDLIST_NAMESTR("AMPG", 1), /* Is ModPHY Power Gate active? */ + }; + + acpigen_write_opregion(&opregion); + acpigen_write_field("PMCP", fieldlist, ARRAY_SIZE(fieldlist), + FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); +} + static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) { + static bool mutex_created; + const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev); static const char *const power_res_states[] = {"_PR0"}; const struct device *parent = dev->bus->dev; @@ -206,6 +276,8 @@ return; } + const enum pcie_rp_type rp_type = soc_get_pcie_rp_type(parent); + /* Read port number of root port that this device is attached to. */ pcie_rp = pci_read_config8(parent, PCH_PCIE_CFG_LCAP_PN); if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) { @@ -218,21 +290,34 @@ printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s)\n", scope, dev_path(parent), config->desc ?: dev->chip_ops->name); + /* Create a mutex for exclusive access to the PMC registers. */ + if (rp_type == PCIE_RP_PCH && !mutex_created) { + acpigen_write_scope("\\_SB.PCI0"); + acpigen_write_mutex("R3MX", 0); + acpigen_write_scope_end(); + mutex_created = true; + } + /* The RTD3 power resource is added to the root port, not the device. */ acpigen_write_scope(scope); if (config->desc) acpigen_write_name_string("_DDN", config->desc); + /* Create OpRegions for MMIO accesses. */ acpigen_write_opregion(&opregion); acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + /* Create the OpRegion to access the ModPHY PG registers (PCH RPs only) */ + if (rp_type == PCIE_RP_PCH) + write_modphy_opregion(pcie_rp); + /* ACPI Power Resource for controlling the attached device power. */ acpigen_write_power_res("RTD3", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); pcie_rtd3_acpi_method_status(pcie_rp, config); - pcie_rtd3_acpi_method_on(pcie_rp, config); - pcie_rtd3_acpi_method_off(pcie_rp, config); + pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type); + pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type); acpigen_pop_len(); /* PowerResource */ /* Indicate to the OS that device supports hotplug in D3. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d Gerrit-Change-Number: 59855 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Define soc_get_pcie_rp_type
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59854 ) Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type ...................................................................... soc/intel/alderlake: Define soc_get_pcie_rp_type In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for alderlake. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 --- M src/soc/intel/alderlake/pcie_rp.c 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59854/1 diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c index 4ec24c2..b2e9e6c 100644 --- a/src/soc/intel/alderlake/pcie_rp.c +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <device/device.h> #include <intelblocks/pcie_rp.h> #include <soc/pci_devs.h> #include <soc/pcie.h> @@ -32,3 +33,36 @@ { return cpu_rp_groups; } + +static bool is_part_of_group(const struct device *dev, + const struct pcie_rp_group *groups) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return false; + + const unsigned int slot_to_find = PCI_SLOT(dev->path.pci.devfn); + const unsigned int fn_to_find = PCI_FUNC(dev->path.pci.devfn); + const struct pcie_rp_group *group; + unsigned int i; + unsigned int fn; + + for (group = groups; group->count; ++group) { + for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) { + if (slot_to_find == group->slot && fn_to_find == fn) + return true; + } + } + + return false; +} + +enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) +{ + if (is_part_of_group(dev, pch_lp_rp_groups)) + return PCIE_RP_PCH; + + if (is_part_of_group(dev, cpu_rp_groups)) + return PCIE_RP_CPU; + + return PCIE_RP_UNKNOWN; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Gerrit-Change-Number: 59854 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Define soc_get_pcie_rp_type
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59853 ) Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type ...................................................................... soc/intel/tigerlake: Define soc_get_pcie_rp_type In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for tigerlake. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 --- M src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/pcie_rp.c 3 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59853/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index f74706e..52eaecf 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -117,4 +117,9 @@ PCIE_RP_PCH, }; +/* + * For PCIe RTD3 support, each SoC that uses it must implement this function. + */ +enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev); + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 6da5e00..25a1d65 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -34,6 +34,7 @@ ramstage-y += lpm.c ramstage-y += me.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += soundwire.c diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c new file mode 100644 index 0000000..f8d4109 --- /dev/null +++ b/src/soc/intel/tigerlake/pcie_rp.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <intelblocks/pcie_rp.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> + +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, + { 0 } +}; + +static const struct pcie_rp_group cpu_rp_groups[] = { + { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1 }, + { .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 1 }, + { .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1 }, + { 0 } +}; + +static bool is_part_of_group(const struct device *dev, + const struct pcie_rp_group *groups) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return false; + + const unsigned int slot_to_find = PCI_SLOT(dev->path.pci.devfn); + const unsigned int fn_to_find = PCI_FUNC(dev->path.pci.devfn); + const struct pcie_rp_group *group; + unsigned int i; + unsigned int fn; + + for (group = groups; group->count; ++group) { + for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) { + if (slot_to_find == group->slot && fn_to_find == fn) + return true; + } + } + + return false; +} + +enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) +{ + if (is_part_of_group(dev, pch_lp_rp_groups)) + return PCIE_RP_PCH; + + if (is_part_of_group(dev, cpu_rp_groups)) + return PCIE_RP_CPU; + + return PCIE_RP_UNKNOWN; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Gerrit-Change-Number: 59853 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59852 ) Change subject: soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h ...................................................................... soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h This enum is useful to have around for more than just the one file, so move it to a common header file, and while we're there, also add an option for UNKNOWN. TEST=boot test on brya0 Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 2 files changed, 11 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/59852/1 diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 121251e..d319abb 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -23,11 +23,6 @@ #define CPU_PCIE_BASE 0x40 -enum pcie_rp_type { - PCH_PCIE_RP, - CPU_PCIE_RP, -}; - enum vtd_base_index_type { VTD_GFX, VTD_IPU, @@ -40,11 +35,11 @@ static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number) { - assert(type == PCH_PCIE_RP || type == CPU_PCIE_RP); + assert(type == PCIE_RP_PCH || type == PCIE_RP_CPU); - if (type == PCH_PCIE_RP) + if (type == PCIE_RP_PCH) return rp_number; - else // type == CPU_PCIE_RP + else // type == PCIE_RP_CPU return CPU_PCIE_BASE + rp_number; } @@ -82,12 +77,12 @@ /* Configure PCH PCIE ports */ m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); - pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp, + pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCIE_RP_PCH, config->pch_pcie_rp, CONFIG_MAX_PCH_ROOT_PORTS); /* Configure CPU PCIE ports */ m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); - pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp, + pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, PCIE_RP_CPU, config->cpu_pcie_rp, CONFIG_MAX_CPU_ROOT_PORTS); } diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 8ed3e3d..f74706e 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -111,4 +111,10 @@ */ uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups); +enum pcie_rp_type { + PCIE_RP_UNKNOWN, + PCIE_RP_CPU, + PCIE_RP_PCH, +}; + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda Gerrit-Change-Number: 59852 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Add #define for Mutex "no timeout" value
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59851 ) Change subject: acpi: Add #define for Mutex "no timeout" value ...................................................................... acpi: Add #define for Mutex "no timeout" value BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I16bc9f3f04dd1e3dc0f3eca3e56377e6f48132b2 --- M src/include/acpi/acpigen.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/59851/1 diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 463c16d..c97713f 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -298,6 +298,8 @@ cppc_entry_t entries[CPPC_MAX_FIELDS_VER_3]; }; +#define ACPI_MUTEX_NO_TIMEOUT 0xffff + void acpigen_write_return_integer(uint64_t arg); void acpigen_write_return_namestr(const char *arg); void acpigen_write_return_string(const char *arg); -- To view, visit https://review.coreboot.org/c/coreboot/+/59851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16bc9f3f04dd1e3dc0f3eca3e56377e6f48132b2 Gerrit-Change-Number: 59851 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST-ONLY / HACK] Mirror payload in RAM before hashing/decompression
by Julius Werner (Code Review) 02 Dec '21

02 Dec '21

Julius Werner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59767 ) Change subject: [TEST-ONLY / HACK] Mirror payload in RAM before hashing/decompression ...................................................................... Abandoned served its purpose -- To view, visit https://review.coreboot.org/c/coreboot/+/59767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9550ad35653f1c949fe1dd83f76142ed3dbad4c Gerrit-Change-Number: 59767 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: cbfs: Remove deprecated APIs
by Julius Werner (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Christian Walter, Werner Zeh, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59682 ) Change subject: cbfs: Remove deprecated APIs ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > With a bit of digging it turned out that on Elkhart Lake FSPS somehow disables BIOS flash caching (c […] Ah great, that is good news. That sounds like a pretty simple explanation then, and hopefully a pretty simple fix. I was worried there might be something more sinister going on. (FWIW I was looking into this mirror_payload() thing, which was added back in CB:5305 but somehow never really used, and I took it out after checking with Aaron in https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/KDE6… , but I never really understood how that worked and whether it was still needed on modern SoCs. Sounds like it's not though, and your issue was just that the caching got incorrectly disabled.) So are you okay with me pushing this while you try to find a fix for Elkhart Lake? FWIW, if nothing else helps it would be possible to do payload mirroring specifically for that SoC by overriding boot_device_ro() in a clever way. But that would be a pretty ugly hack and just working around the actual issue, fixing the MTRR would definitely be the better option. -- To view, visit https://review.coreboot.org/c/coreboot/+/59682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Gerrit-Change-Number: 59682 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 23:16:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2021