coreboot-gerrit December 2021

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Change in coreboot[master]: cbfs: Remove deprecated APIs
by Arthur Heymans (Code Review) 06 Dec '21

06 Dec '21

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59682 ) Change subject: cbfs: Remove deprecated APIs ...................................................................... Patch Set 5: (1 comment) Patchset: PS2: > Yes, I am OK with this patch and I will have a look at the MTRR thing on Elkhart Lake. Since this is the root cause it needs to be fixed anyway. Try https://review.coreboot.org/c/coreboot/+/59845 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/59682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Gerrit-Change-Number: 59682 Gerrit-PatchSet: 5 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 13:09:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
by Arthur Heymans (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Arthur Heymans, Nico Huber, Paul Menzel, Ravindra, Sridhar Siricilla, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 ) Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/59359/comment/a2ba57fb_4abee3f8 PS7, Line 393: acpi_write_xppc_method This is a bit weird. Why not generate it on a different scope than cpu 0 and call it from all CPUs instead of adding all the logic around core_id ==/!-= 0? -- To view, visit https://review.coreboot.org/c/coreboot/+/59359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Gerrit-Change-Number: 59359 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 12:49:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: complete devapc settings
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59746 ) Change subject: soc/mediatek/mt8195: complete devapc settings ...................................................................... soc/mediatek/mt8195: complete devapc settings In previous patch (CB:56764), only basic settings were added. Now complete devapc settings on MT8195. 1. Update permission setting 2. Updtate master domain setting: - domain 1: PCIE0, PCIE1 - domain 2: SPM, SSPM, CPU_EB 3. Set domain remap - MMSYS (4-bit to 2-bit) - TINYSYS (4-bit to 3-bit) - TINYSYS (3-bit to 4-bit) - TINYSYS to EMI (3-bit to 4-bit) - INFRA2 (3-bit to 4-bit) 4. Set SCP domain and ADSP domain - domain 3: SCP - domain 4: ADSP BUG=b:204347737 TEST=sanity test pass Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59746 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h M src/soc/mediatek/mt8195/include/soc/devapc.h 3 files changed, 274 insertions(+), 142 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/devapc.c b/src/soc/mediatek/mt8195/devapc.c index c41b1ac..1b0de8c 100644 --- a/src/soc/mediatek/mt8195/devapc.c +++ b/src/soc/mediatek/mt8195/devapc.c @@ -7,7 +7,7 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { /* 0 */ DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-1", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-2", @@ -15,26 +15,26 @@ DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-4", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION3, FORBIDDEN11), DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S-1", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION3, FORBIDDEN11), DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_MEM_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN11), DAPC_INFRA_AO_SYS0_ATTR("PERICFG_AO_APB_S", NO_PROTECTION, FORBIDDEN15), /* 10 */ DAPC_INFRA_AO_SYS0_ATTR("GPIO_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION2, FORBIDDEN12), DAPC_INFRA_AO_SYS0_ATTR("TOPRGU_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DSP_IRQ_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN11), DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_INFRA_AO_APB_S", - SEC_RW_ONLY, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("BCRM_INFRA_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DEBUG_CTRL_INFRA_AO_APB_S", @@ -42,16 +42,14 @@ DAPC_INFRA_AO_SYS0_ATTR("AP_CIRQ_EINT_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMIC_WRAP_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("KP_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("TOP_MISC_APB_S", NO_PROTECTION, FORBIDDEN15), /* 20 */ DAPC_INFRA_AO_SYS0_ATTR("DVFSRC_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MBIST_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("HDMI_CEC_APB_S", @@ -63,19 +61,16 @@ DAPC_INFRA_AO_SYS0_ATTR("IRRX_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("SYS_TIMER_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MODEM_TEMP_SHARE_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMIF1_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMICSPI_MST_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), /* 30 */ DAPC_INFRA_AO_SYS0_ATTR("TIA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_INFRA_CFG_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DRM_DEBUG_TOP_APB_S", @@ -91,15 +86,14 @@ DAPC_INFRA_AO_SYS0_ATTR("SECURITY_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("SPMI_MST_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DEBUG_CTRL_FMEM_AO_APB_S", NO_PROTECTION, FORBIDDEN15), /* 40 */ DAPC_INFRA_AO_SYS0_ATTR("BCRM_FMEM_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_FMEM_AO_APB_S", - SEC_RW_ONLY, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PWM_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMSR_APB_S", @@ -141,13 +135,13 @@ DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-1", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-2", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-3", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-4", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("L3C_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("L3C_S-1", @@ -160,11 +154,11 @@ NO_PROTECTION, FORBIDDEN15), /* 70 */ DAPC_INFRA_AO_SYS0_ATTR("NNA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("PCIE0_AXI_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION2, FORBIDDEN14), DAPC_INFRA_AO_SYS0_ATTR("PCIE1_AXI_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION2, FORBIDDEN14), DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB0_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB1_S", @@ -180,42 +174,42 @@ static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = { /* 0 */ DAPC_INFRA_AO_SYS1_ATTR("MM_S_S", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-1", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-2", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-3", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-4", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-5", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-6", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-7", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-8", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-9", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), /* 10 */ DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-10", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-11", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-12", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-13", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-14", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-15", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-16", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-17", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-18", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-19", @@ -232,7 +226,7 @@ DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-24", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-25", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-26", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-27", @@ -1100,34 +1094,34 @@ static const struct apc_infra_peri_dom_16 peri_ao_sys0_devices[] = { /* 0 */ DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_PERI_AO_APB_S", - SEC_RW_ONLY, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("BCRM_PERI_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_PERI_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-1", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-2", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-3", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-4", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-5", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-6", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), /* 10 */ DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-7", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-8", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-9", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-10", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("SSUSB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-1", @@ -1135,83 +1129,79 @@ DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-2", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("DEBUGSYS_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S-1", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN2, + NO_PROTECTION, FORBIDDEN10), /* 20 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S-1", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN2, + NO_PROTECTION, FORBIDDEN10), DAPC_PERI_AO_SYS0_ATTR("NOR_AXI_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), /* 30 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), /* 40 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), /* 50 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("CCIF2_AP_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("CCIF2_MD_APB_S", @@ -1240,7 +1230,7 @@ static const struct apc_infra_peri_dom_8 peri_ao_sys1_devices[] = { /* 0 */ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-1", NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-2", @@ -1252,22 +1242,22 @@ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-5", NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-6", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-7", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-8", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-9", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), /* 10 */ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-10", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-11", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-12", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-13", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-14", NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-15", @@ -1275,18 +1265,18 @@ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-16", NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-17", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-18", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-19", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), /* 20 */ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-20", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-21", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-22", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), }; static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = { @@ -1300,7 +1290,7 @@ DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB0_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB1_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB2_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB3_S", @@ -1449,8 +1439,7 @@ DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_PDN_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("TRNG_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("GCPU_APB_S", @@ -1488,10 +1477,9 @@ DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB4_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("EMI_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_APB_S", - NO_PROTECTION, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("DEVICE_MPU_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("APDMA_APB_S", @@ -1520,8 +1508,7 @@ DAPC_PERI2_AO_SYS0_ATTR("PERI_SLOW_M_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("EMI_SUB_INFRA_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_SUB_INFRA_APB_S", NO_PROTECTION, FORBIDDEN15), /* 110 */ @@ -1530,8 +1517,7 @@ DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_SUB_INFRA_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_MEM_SUB_INFRA_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("BCRM_SUB_INFRA_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("DEBUG_CTRL_SUB_INFRA_AO_APB_S", @@ -1543,7 +1529,7 @@ DAPC_PERI2_AO_SYS0_ATTR("SSC_SUB_INFRA_APB2_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_AO_MEM_SUB_INFRA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN11), DAPC_PERI2_AO_SYS0_ATTR("SUB_FAKE_ENGINE_MM_S", NO_PROTECTION, FORBIDDEN15), /* 120 */ @@ -1570,9 +1556,9 @@ DAPC_PERI_PAR_AO_SYS0_ATTR("MSDC2_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("PCIE0_AHB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION2, FORBIDDEN14), DAPC_PERI_PAR_AO_SYS0_ATTR("PCIE1_AHB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION2, FORBIDDEN14), DAPC_PERI_PAR_AO_SYS0_ATTR("SSUSB_P1_S", NO_PROTECTION, FORBIDDEN15), /* 10 */ @@ -1583,7 +1569,7 @@ DAPC_PERI_PAR_AO_SYS0_ATTR("AUXADC_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("UART0_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_PAR_AO_SYS0_ATTR("UART1_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("UART2_APB_S", @@ -1598,7 +1584,7 @@ NO_PROTECTION, FORBIDDEN15), /* 20 */ DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_PAR_AO_SYS0_ATTR("PERI_MBIST_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("DISP_PWM_APB_S", @@ -1633,9 +1619,9 @@ DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_PDN_APB_S", - SEC_RW_ONLY, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL2_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB_S", NO_PROTECTION, FORBIDDEN15), /* 40 */ @@ -1768,6 +1754,9 @@ printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO)MAS_SEC_0: %#x\n", read32(getreg(base, MAS_SEC_0))); + + printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO %#lx)DOM_REMAP_0_0: %#x\n", + base, read32(getreg(base, DOM_REMAP_0_0))); } static void dump_peri_ao_apc(uintptr_t base) @@ -1818,19 +1807,91 @@ read32(getreg(base, MAS_SEC_0))); } +static void dump_fmem_ao(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_FMEM_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n", + base, read32(getreg(base, DOM_REMAP_0_0))); +} + +static void dump_infra2_ao_apc(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_INFRA2_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n", + base, read32(getreg(base, DOM_REMAP_0_0))); +} + +static void dump_scp_master(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] SCP:%#x ADSP:%#x Lock:%#x\n", + read32(getreg(base, SCP_DOM)), + read32(getreg(base, ADSP_DOM)), + read32(getreg(base, ONETIME_LOCK))); +} + static void infra_init(uintptr_t base) { /* Side band */ SET32_BITFIELDS(getreg(base, MAS_SEC_0), CPU_EB_SEC, SECURE_TRANS); + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_0), + SCP_SSPM_DOM, DOMAIN_2, + CPU_EB_DOM, DOMAIN_2); + /* Default APC Setting */ set_infra_ao_apc(base); + + /* + * Domain Remap: MMSYS slave domain remap (4-bit to 2-bit) + * 1. From domain 0 to domain 0 (no protection for all) + * 2. From domain 1, 2, 4, 5 to domain 1 (forbidden for all) + * 3. From domain 3 to domain 3 + * 4. others from XXX to domain 0 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_2_0), + TWO_BIT_DOM_REMAP_0, DOMAIN_0, + TWO_BIT_DOM_REMAP_1, DOMAIN_1, + TWO_BIT_DOM_REMAP_2, DOMAIN_1, + TWO_BIT_DOM_REMAP_3, DOMAIN_3, + TWO_BIT_DOM_REMAP_4, DOMAIN_1, + TWO_BIT_DOM_REMAP_5, DOMAIN_1); + /* + * Domain Remap: TINYSYS (3-bit to 4-bit) + * 1. SCP from 3 to 3 + * 2. DSP from 4 to 4 + * 3. others from XXX to 15 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, DOMAIN_15, + FOUR_BIT_DOM_REMAP_1, DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, DOMAIN_3, + FOUR_BIT_DOM_REMAP_4, DOMAIN_4, + FOUR_BIT_DOM_REMAP_5, DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, DOMAIN_15); } static void peri_init(uintptr_t base) { /* Default APC Setting */ set_peri_ao_apc(base); + + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_0), SPM_DOM, DOMAIN_2); + + /* + * Domain Remap: TINYSYS slave domain remap (4-bit to 3-bit) + * 1. From domain 0 to domain 0 (no protection for all) + * 2. From domain 1 ~ 5 to domain 1 ~ 5 + * 3. others from XXX to domain 0 (no protection for all) + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + THREE_BIT_DOM_REMAP_0, DOMAIN_0, + THREE_BIT_DOM_REMAP_1, DOMAIN_1, + THREE_BIT_DOM_REMAP_2, DOMAIN_2, + THREE_BIT_DOM_REMAP_3, DOMAIN_3, + THREE_BIT_DOM_REMAP_4, DOMAIN_4, + THREE_BIT_DOM_REMAP_5, DOMAIN_5); } static void peri2_init(uintptr_t base) @@ -1850,10 +1911,56 @@ SSUSB_P2_SEC, SECURE_TRANS, SSUSB_P3_SEC, SECURE_TRANS); + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_4), + PCIE0_DOM, DOMAIN_1, + PCIE1_DOM, DOMAIN_1); + /* Default APC Setting */ set_peri_par_ao_apc(base); } +static void fmem_master_init(uintptr_t base) +{ + /* + * Domain Remap: TINYSYS to EMI (3-bit to 4-bit) + * 1. SCP from 3 to 3 + * 2. DSP from 4 to 4 + * 3. others from XXX to 15 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, DOMAIN_15, + FOUR_BIT_DOM_REMAP_1, DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, DOMAIN_3, + FOUR_BIT_DOM_REMAP_4, DOMAIN_4, + FOUR_BIT_DOM_REMAP_5, DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, DOMAIN_15); +} + +static void infra2_init(uintptr_t base) +{ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, DOMAIN_15, + FOUR_BIT_DOM_REMAP_1, DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, DOMAIN_3, + FOUR_BIT_DOM_REMAP_4, DOMAIN_4, + FOUR_BIT_DOM_REMAP_5, DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, DOMAIN_15); +} + +static void scp_master_init(uintptr_t base) +{ + write32(getreg(base, SCP_DOM), DOMAIN_3); + write32(getreg(base, ADSP_DOM), DOMAIN_4); + + /* Let SCP_DOM and ADSP_DOM registers be read-only for security */ + write32(getreg(base, ONETIME_LOCK), 0x5); +} + struct devapc_init_ops { uintptr_t base; void (*init)(uintptr_t base); @@ -1863,6 +1970,9 @@ { DEVAPC_PERI_AO_BASE, peri_init, dump_peri_ao_apc }, { DEVAPC_PERI2_AO_BASE, peri2_init, dump_peri2_ao_apc }, { DEVAPC_PERI_PAR_AO_BASE, peri_par_init, dump_peri_par_ao_apc }, + { DEVAPC_FMEM_AO_BASE, fmem_master_init, dump_fmem_ao }, + { DEVAPC_INFRA2_AO_BASE, infra2_init, dump_infra2_ao_apc }, + { SCP_CFG_BASE, scp_master_init, dump_scp_master }, }; void dapc_init(void) diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index d9486b3..e5fd822 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -43,6 +43,7 @@ I2C_DMA_BASE = IO_PHYS + 0x00220080, EMI1_SUB_BASE = IO_PHYS + 0x00225000, EMI0_MPU_BASE = IO_PHYS + 0x00226000, + DEVAPC_INFRA2_AO_BASE = IO_PHYS + 0x00228000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, INFRA_TRACKER_BASE = IO_PHYS + 0x00314000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, diff --git a/src/soc/mediatek/mt8195/include/soc/devapc.h b/src/soc/mediatek/mt8195/include/soc/devapc.h index df81972..5267b3b 100644 --- a/src/soc/mediatek/mt8195/include/soc/devapc.h +++ b/src/soc/mediatek/mt8195/include/soc/devapc.h @@ -17,10 +17,17 @@ DOM_REMAP_1_1 = 0x814, DOM_REMAP_2_0 = 0x820, MAS_DOM_0 = 0x0900, + MAS_DOM_4 = 0x0910, MAS_SEC_0 = 0x0A00, AO_APC_CON = 0x0F00, }; +enum scp_offset { + SCP_DOM = 0xA5080, + ADSP_DOM = 0xA5088, + ONETIME_LOCK = 0xA5104, +}; + /****************************************************************************** * STRUCTURE DEFINITION ******************************************************************************/ @@ -96,18 +103,23 @@ PERM_ATTR12, PERM_ATTR13, \ PERM_ATTR14, PERM_ATTR15) +#define NO_PROTECTION2 NO_PROTECTION, NO_PROTECTION +#define NO_PROTECTION3 NO_PROTECTION2, NO_PROTECTION + +#define FORBIDDEN2 FORBIDDEN, FORBIDDEN #define FORBIDDEN3 FORBIDDEN, FORBIDDEN, FORBIDDEN #define FORBIDDEN7 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ FORBIDDEN, FORBIDDEN -#define FORBIDDEN12 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ +#define FORBIDDEN10 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN -#define FORBIDDEN13 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN +#define FORBIDDEN11 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN -#define FORBIDDEN15 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN + FORBIDDEN +#define FORBIDDEN12 FORBIDDEN11, FORBIDDEN +#define FORBIDDEN13 FORBIDDEN12, FORBIDDEN +#define FORBIDDEN14 FORBIDDEN13, FORBIDDEN +#define FORBIDDEN15 FORBIDDEN14, FORBIDDEN enum devapc_sys_dom_num { DOM_NUM_INFRA_AO_SYS0 = 16, @@ -144,6 +156,10 @@ DEFINE_BIT(CPU_EB_SEC, 1) DEFINE_BITFIELD(CPU_EB_DOM, 11, 8) /* 1 */ +DEFINE_BITFIELD(SCP_SSPM_DOM, 19, 16) /* 2 */ + +/* PERI */ +DEFINE_BITFIELD(SPM_DOM, 11, 8) /* 1 */ /* PERI_PAR */ DEFINE_BIT(SSUSB_SEC, 21) @@ -153,6 +169,9 @@ DEFINE_BIT(SSUSB_P2_SEC, 3) DEFINE_BIT(SSUSB_P3_SEC, 4) +DEFINE_BITFIELD(PCIE0_DOM, 11, 8) /* 17 */ +DEFINE_BITFIELD(PCIE1_DOM, 19, 16) /* 18 */ + /* Domain Remap */ DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_0, 3, 0) DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_1, 7, 4) @@ -168,11 +187,13 @@ DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_2, 8, 6) DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_3, 11, 9) DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_4, 14, 12) +DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_5, 17, 15) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_0, 1, 0) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_1, 3, 2) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_2, 5, 4) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_3, 7, 6) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_4, 9, 8) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_0, 1, 0) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_1, 3, 2) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_2, 5, 4) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_3, 7, 6) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_4, 9, 8) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_5, 11, 10) #endif /* SOC_MEDIATEK_MT8195_DEVAPC_H */ 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add support for ADL-N CPU Type
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59836 ) Change subject: soc/intel/alderlake: Add support for ADL-N CPU Type ...................................................................... soc/intel/alderlake: Add support for ADL-N CPU Type Add Alder Lake-N case for adl_cpu_type and get_supported_lpm_mask. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59836 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/include/soc/cpu.h 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, but someone else must approve Kangheui Won: Looks good to me, approved diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 94658c7..be11527 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -168,6 +168,11 @@ PCI_DEVICE_ID_INTEL_ADL_S_ID_15, }; + const uint16_t adl_n_mch_ids[] = { + PCI_DEVICE_ID_INTEL_ADL_N_ID_1, + PCI_DEVICE_ID_INTEL_ADL_N_ID_2, + }; + const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT), PCI_FUNC(SA_DEVFN_ROOT)), PCI_DEVICE_ID); @@ -187,6 +192,11 @@ return ADL_S; } + for (size_t i = 0; i < ARRAY_SIZE(adl_n_mch_ids); i++) { + if (adl_n_mch_ids[i] == mchid) + return ADL_N; + } + return ADL_UNKNOWN; } @@ -195,6 +205,7 @@ enum adl_cpu_type type = get_adl_cpu_type(); switch (type) { case ADL_M: /* fallthrough */ + case ADL_N: case ADL_P: return LPM_S0i2_0 | LPM_S0i3_0; case ADL_S: diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index 233e0c2..cd6f34f 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -22,6 +22,7 @@ enum adl_cpu_type { ADL_UNKNOWN, ADL_M, + ADL_N, ADL_P, ADL_S, }; 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d Gerrit-Change-Number: 59836 Gerrit-PatchSet: 4 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: northbridge/amd/pi/00730F01: enable PARALLEL_MP
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59808 ) Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP ...................................................................... northbridge/amd/pi/00730F01: enable PARALLEL_MP Disable LEGACY_SMP_INIT to enable PARALLEL_MP. Also remove a large amount of APIC code that is now unnecessary. TEST=Boot on PC Engines apu3 Boot time reduced from 1.707 seconds to 1.620 seconds average across 5 coldboots. Inspired by CB:59693 Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59808 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/pi/00730F01/model_16_init.c M src/northbridge/amd/pi/00730F01/Kconfig M src/northbridge/amd/pi/00730F01/northbridge.c 3 files changed, 27 insertions(+), 127 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index a5a8064..f84b03a 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -23,21 +23,6 @@ msr_t msr; u32 siblings; - /* - * All cores are initialized sequentially, so the solution for APs will be created - * before they start. - */ - x86_setup_mtrrs_with_detect(); - /* - * Enable ROM caching on BSP we just lost when creating MTRR solution, for faster - * execution of e.g. AmdInitLate - */ - if (boot_cpu()) { - mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); - } - x86_mtrr_check(); - /* zero the machine check error status registers */ mca_clear_status(); diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index 27ae673..94abb93 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -2,7 +2,6 @@ config NORTHBRIDGE_AMD_PI_00730F01 bool - select LEGACY_SMP_INIT if NORTHBRIDGE_AMD_PI_00730F01 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 332bf1ac..b56e9ca 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -13,7 +13,7 @@ #include <string.h> #include <stdlib.h> #include <lib.h> -#include <cpu/cpu.h> +#include <cpu/x86/mp.h> #include <Porting.h> #include <AGESA.h> #include <Topology.h> @@ -864,22 +864,7 @@ static void cpu_bus_scan(struct device *dev) { - struct bus *cpu_bus; struct device *dev_mc; - int i,j; - int coreid_bits; - int core_max = 0; - unsigned int ApicIdCoreIdSize; - unsigned int core_nums; - int siblings = 0; - unsigned int family; - u32 modules = 0; - int ioapic_count = 0; - - /* For binaryPI there is no multiprocessor configuration, the number of - * modules will always be 1. */ - modules = 1; - ioapic_count = CONFIG_NUM_OF_IOAPICS; dev_mc = pcidev_on_root(DEV_CDB, 0); if (!dev_mc) { @@ -887,109 +872,40 @@ die(""); } sysconf_init(dev_mc); - - /* Get Max Number of cores(MNC) */ - coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; - core_max = 1 << (coreid_bits & 0x000F); //mnc - - ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); - if (ApicIdCoreIdSize) { - core_nums = (1 << ApicIdCoreIdSize) - 1; - } else { - core_nums = 3; //quad core - } - - /* Find which cpus are present */ - cpu_bus = dev->link_list; - for (i = 0; i < node_nums; i++) { - struct device *cdb_dev; - unsigned int devn; - struct bus *pbus; - - devn = DEV_CDB + i; - pbus = dev_mc->bus; - - /* Find the cpu's pci device */ - cdb_dev = pcidev_on_root(devn, 0); - if (!cdb_dev) { - /* If I am probing things in a weird order - * ensure all of the cpu's pci devices are found. - */ - int fn; - for (fn = 0; fn <= 5; fn++) { //FBDIMM? - cdb_dev = pci_probe_dev(NULL, pbus, - PCI_DEVFN(devn, fn)); - } - cdb_dev = pcidev_on_root(devn, 0); - } else { - /* Ok, We need to set the links for that device. - * otherwise the device under it will not be scanned - */ - - add_more_links(cdb_dev, 4); - } - - family = cpuid_eax(1); - family = (family >> 20) & 0xFF; - if (family == 1) { //f10 - u32 dword; - cdb_dev = pcidev_on_root(devn, 3); - dword = pci_read_config32(cdb_dev, 0xe8); - siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); - } else if (family == 7) {//f16 - cdb_dev = pcidev_on_root(devn, 5); - if (cdb_dev && cdb_dev->enabled) { - siblings = pci_read_config32(cdb_dev, 0x84); - siblings &= 0xFF; - } - } else { - siblings = 0; //default one core - } - int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", - dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - - for (j = 0; j <= siblings; j++) { - u32 lapicid_start = 0; - - /* - * APIC ID calculation is tightly coupled with AGESA v5 code. - * This calculation MUST match the assignment calculation done - * in LocalApicInitializationAtEarly() function. - * And reference GetLocalApicIdForCore() - * - * Apply APIC enumeration rules - * For systems with >= 16 APICs, put the IO-APICs at 0..n and - * put the local-APICs at m..z - * - * This is needed because many IO-APIC devices only have 4 bits - * for their APIC id and therefore must reside at 0..15 - */ - if ((node_nums * core_max) + ioapic_count >= 0x10) { - lapicid_start = (ioapic_count - 1) / core_max; - lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); - } - u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", - i, j, apic_id); - - struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); - if (cpu) - amd_cpu_topology(cpu, i, j); - } //j - } } -static void cpu_bus_init(struct device *dev) +static void pre_mp_init(void) { - initialize_cpus(dev->link_list); + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_cpu_count(void) +{ + uint8_t siblings = cpuid_ecx(0x80000008) & 0xff; + + return siblings + 1; +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, +}; + +void mp_init_cpus(struct bus *cpu_bus) +{ + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); + + /* The flash is now no longer cacheable. Reset to WP for performance. */ + mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); } static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = cpu_bus_init, + .init = mp_cpu_bus_init, .scan_bus = cpu_bus_scan, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Gerrit-Change-Number: 59808 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: x86_64 assembly: Don't touch %gs
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59764 ) Change subject: x86_64 assembly: Don't touch %gs ...................................................................... x86_64 assembly: Don't touch %gs With CPU_INFO_V2 enabled %gs holds the pointer to the cpu_info struct, so don't clobber it. Backup and restore %gs where possible. Fixes a crash in MPinit seen after calling FSP-S. Change-Id: If9fc999b34530de5d8b6ad27b9af25fc552e9420 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59764 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/64bit/exit32.inc M src/cpu/x86/64bit/mode_switch.S M src/security/intel/txt/getsec_enteraccs.S 3 files changed, 16 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc index 4d1149e..3ac86a9 100644 --- a/src/cpu/x86/64bit/exit32.inc +++ b/src/cpu/x86/64bit/exit32.inc @@ -68,7 +68,6 @@ movl %eax, %es movl %eax, %ss movl %eax, %fs - movl %eax, %gs /* Disable paging. */ movl %cr0, %eax diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S index eea104b..c27f540 100644 --- a/src/cpu/x86/64bit/mode_switch.S +++ b/src/cpu/x86/64bit/mode_switch.S @@ -15,6 +15,10 @@ push %r14 push %r15 + /* Backup gs to stack */ + movl %gs, %eax + push %rax + /* Arguments to stack */ push %rdi push %rsi @@ -23,9 +27,9 @@ #include <cpu/x86/64bit/exit32.inc> - movl -48(%ebp), %eax /* Argument count */ - movl -64(%ebp), %edx /* Argument 0 */ - movl -72(%ebp), %ecx /* Argument 1 */ + movl -56(%ebp), %eax /* Argument count */ + movl -72(%ebp), %edx /* Argument 0 */ + movl -80(%ebp), %ecx /* Argument 1 */ /* Align the stack */ andl $0xFFFFFFF0, %esp @@ -46,7 +50,7 @@ pushl %edx /* Argument 0 */ 1: - movl -56(%ebp), %ebx /* Function to call */ + movl -64(%ebp), %ebx /* Function to call */ call *%ebx movl %eax, %ebx @@ -57,6 +61,8 @@ movl %ebx, %eax /* Restore registers */ + mov -48(%rbp), %rbx + movl %ebx, %gs mov -40(%rbp), %r15 mov -32(%rbp), %r14 mov -24(%rbp), %r13 diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index 09f9f38..cbb24b6 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -227,6 +227,10 @@ movd %esp, %xmm0 movd %ebp, %xmm1 + /* Backup %gs used by CPU_INFO_V2 */ + movl %gs, %eax + movd %eax, %xmm2 + /* * Get function arguments. * It's important to pass the exact ACM size as it's used by getsec to verify @@ -261,6 +265,8 @@ movl %eax, %es movl %eax, %ss movl %eax, %fs + /* Restore %gs used by CPU_INFO_V2 */ + movd %xmm2, %eax movl %eax, %gs /* Disable cache */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9fc999b34530de5d8b6ad27b9af25fc552e9420 Gerrit-Change-Number: 59764 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: security/intel: Use defines for segment registers
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59763 ) Change subject: security/intel: Use defines for segment registers ...................................................................... security/intel: Use defines for segment registers Change-Id: I6f11039bafa3800d59d61defa8824ae962224c9b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59763 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/intel/txt/getsec_enteraccs.S 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index be3a1b4..09f9f38 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -3,6 +3,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> +#include <arch/ram_segs.h> #include "getsec_mtrr_setup.inc" @@ -252,10 +253,10 @@ lgdt -48(%ebp) /* Set cs */ - ljmp $0x10, $1f + ljmp $RAM_CODE_SEG, $1f 1: /* Fix segment registers */ - movl $0x18, %eax + movl $RAM_DATA_SEG, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f11039bafa3800d59d61defa8824ae962224c9b Gerrit-Change-Number: 59763 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: security/intel: Use defines for segment registers
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Patrick Rudolph, Paul Menzel. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59763 ) Change subject: security/intel: Use defines for segment registers ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59763/comment/b40b4c6c_ed95e5dc PS1, Line 7: src/ > Not needed. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f11039bafa3800d59d61defa8824ae962224c9b Gerrit-Change-Number: 59763 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 12:37:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: security/intel: Use defines for segment registers
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Patrick Rudolph. Patrick Georgi has uploaded a new patch set (#2) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/59763 ) Change subject: security/intel: Use defines for segment registers ...................................................................... security/intel: Use defines for segment registers Change-Id: I6f11039bafa3800d59d61defa8824ae962224c9b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/intel/txt/getsec_enteraccs.S 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/59763/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f11039bafa3800d59d61defa8824ae962224c9b Gerrit-Change-Number: 59763 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cbfs: Remove deprecated APIs
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59682 ) Change subject: cbfs: Remove deprecated APIs ...................................................................... cbfs: Remove deprecated APIs This patch removes all remaining pieces of the old CBFS API, now that the last straggling use cases of it have been ported to the new one (meaning cbfs_map()/cbfs_load()/etc... see CB:39304 and CB:38421). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59682 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/commonlib/Makefile.inc D src/commonlib/cbfs.c D src/commonlib/include/commonlib/cbfs.h M src/include/cbfs.h M src/lib/cbfs.c M src/security/tpm/tspi/crtm.h M src/security/vboot/Kconfig M tests/lib/cbfs-lookup-test.c M tests/lib/cbfs-verification-test.c 9 files changed, 5 insertions(+), 483 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Raul Rangel: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 9347f88..2477e07 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -27,13 +27,6 @@ endif ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c -bootblock-y += cbfs.c -verstage-y += cbfs.c -romstage-y += cbfs.c -ramstage-y += cbfs.c -smm-y += cbfs.c -postcar-y += cbfs.c - bootblock-y += bsd/cbfs_private.c verstage-y += bsd/cbfs_private.c romstage-y += bsd/cbfs_private.c diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c deleted file mode 100644 index e7f800c..0000000 --- a/src/commonlib/cbfs.c +++ /dev/null @@ -1,347 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <commonlib/cbfs.h> -#include <commonlib/endian.h> -#include <commonlib/helpers.h> -#include <string.h> -#include <vb2_sha.h> - -static size_t cbfs_next_offset(const struct region_device *cbfs, - const struct cbfsf *f) -{ - size_t offset; - - if (f == NULL) - return 0; - - /* The region_device objects store absolute offsets over the whole - * region. Therefore a relative offset needs to be calculated. */ - offset = rdev_relative_offset(cbfs, &f->data); - offset += region_device_sz(&f->data); - - return ALIGN_UP(offset, CBFS_ALIGNMENT); -} - -static int cbfs_end(const struct region_device *cbfs, size_t offset) -{ - if (offset >= region_device_sz(cbfs)) - return 1; - - return 0; -} - -int cbfs_for_each_file(const struct region_device *cbfs, - const struct cbfsf *prev, struct cbfsf *fh) -{ - size_t offset; - - offset = cbfs_next_offset(cbfs, prev); - - /* Try to scan the entire cbfs region looking for file name. */ - while (1) { - struct cbfs_file file; - const size_t fsz = sizeof(file); - - DEBUG("Checking offset %zx\n", offset); - - /* End of region. */ - if (cbfs_end(cbfs, offset)) - return 1; - - /* Can't read file. Nothing else to do but bail out. */ - if (rdev_readat(cbfs, &file, offset, fsz) != fsz) - break; - - if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) { - offset++; - offset = ALIGN_UP(offset, CBFS_ALIGNMENT); - continue; - } - - file.len = read_be32(&file.len); - file.offset = read_be32(&file.offset); - - DEBUG("File @ offset %zx size %x\n", offset, file.len); - - /* Keep track of both the metadata and the data for the file. */ - if (rdev_chain(&fh->metadata, cbfs, offset, file.offset)) - break; - - if (rdev_chain(&fh->data, cbfs, offset + file.offset, file.len)) - break; - - /* Success. */ - return 0; - } - - return -1; -} - -size_t cbfs_for_each_attr(void *metadata, size_t metadata_size, - size_t last_offset) -{ - struct cbfs_file_attribute *attr; - - if (!last_offset) { - struct cbfs_file *file = metadata; - size_t start_offset = read_be32(&file->attributes_offset); - if (start_offset <= sizeof(struct cbfs_file) || - start_offset + sizeof(*attr) > metadata_size) - return 0; - return start_offset; - } - - attr = metadata + last_offset; - size_t next_offset = last_offset + read_be32(&attr->len); - - if (next_offset + sizeof(*attr) > metadata_size) - return 0; - return next_offset; -} - -int cbfsf_decompression_info(struct cbfsf *fh, uint32_t *algo, size_t *size) -{ - size_t metadata_size = region_device_sz(&fh->metadata); - void *metadata = rdev_mmap_full(&fh->metadata); - size_t offs = 0; - - if (!metadata) - return -1; - - while ((offs = cbfs_for_each_attr(metadata, metadata_size, offs))) { - struct cbfs_file_attr_compression *attr = metadata + offs; - if (read_be32(&attr->tag) != CBFS_FILE_ATTR_TAG_COMPRESSION) - continue; - - *algo = read_be32(&attr->compression); - *size = read_be32(&attr->decompressed_size); - rdev_munmap(&fh->metadata, metadata); - return 0; - } - - *algo = CBFS_COMPRESS_NONE; - *size = region_device_sz(&fh->data); - rdev_munmap(&fh->metadata, metadata); - return 0; -} - -int cbfsf_file_type(struct cbfsf *fh, uint32_t *ftype) -{ - const size_t sz = sizeof(*ftype); - - if (rdev_readat(&fh->metadata, ftype, - offsetof(struct cbfs_file, type), sz) != sz) - return -1; - - *ftype = read_be32(ftype); - - return 0; -} - -int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, - const char *name, uint32_t *type) -{ - struct cbfsf *prev; - - LOG("Locating '%s'\n", name); - - prev = NULL; - - while (1) { - int ret; - char *fname; - int name_match; - const size_t fsz = sizeof(struct cbfs_file); - - ret = cbfs_for_each_file(cbfs, prev, fh); - prev = fh; - - /* Either failed to read or hit the end of the region. */ - if (ret < 0 || ret > 0) - break; - - fname = rdev_mmap(&fh->metadata, fsz, - region_device_sz(&fh->metadata) - fsz); - - if (fname == NULL) - break; - - name_match = !strcmp(fname, name); - rdev_munmap(&fh->metadata, fname); - - if (!name_match) { - DEBUG(" Unmatched '%s' at %zx\n", fname, - rdev_relative_offset(cbfs, &fh->metadata)); - continue; - } - - if (type != NULL) { - uint32_t ftype; - - if (cbfsf_file_type(fh, &ftype)) - break; - - if (*type != 0 && *type != ftype) { - DEBUG(" Unmatched type %x at %zx\n", ftype, - rdev_relative_offset(cbfs, - &fh->metadata)); - continue; - } - // *type being 0 means we want to know ftype. - // We could just do a blind assignment but - // if type is pointing to read-only memory - // that might be bad. - if (*type == 0) - *type = ftype; - } - - LOG("Found @ offset %zx size %zx\n", - rdev_relative_offset(cbfs, &fh->metadata), - region_device_sz(&fh->data)); - - /* Success. */ - return 0; - } - - LOG("'%s' not found.\n", name); - return -1; -} - -static int cbfs_extend_hash_buffer(struct vb2_digest_context *ctx, - void *buf, size_t sz) -{ - return vb2_digest_extend(ctx, buf, sz); -} - -static int cbfs_extend_hash(struct vb2_digest_context *ctx, - const struct region_device *rdev) -{ - uint8_t buffer[1024]; - size_t sz_left; - size_t offset; - - sz_left = region_device_sz(rdev); - offset = 0; - - while (sz_left) { - int rv; - size_t block_sz = MIN(sz_left, sizeof(buffer)); - - if (rdev_readat(rdev, buffer, offset, block_sz) != block_sz) - return VB2_ERROR_UNKNOWN; - - rv = cbfs_extend_hash_buffer(ctx, buffer, block_sz); - - if (rv) - return rv; - - sz_left -= block_sz; - offset += block_sz; - } - - return VB2_SUCCESS; -} - -/* Include offsets of child regions within the parent into the hash. */ -static int cbfs_extend_hash_with_offset(struct vb2_digest_context *ctx, - const struct region_device *p, - const struct region_device *c) -{ - int32_t soffset; - int rv; - - soffset = rdev_relative_offset(p, c); - - if (soffset < 0) - return VB2_ERROR_UNKNOWN; - - /* All offsets in big endian format. */ - write_be32(&soffset, soffset); - - rv = cbfs_extend_hash_buffer(ctx, &soffset, sizeof(soffset)); - - if (rv) - return rv; - - return cbfs_extend_hash(ctx, c); -} - -/* Hash in the potential CBFS header sitting at the beginning of the CBFS - * region as well as relative offset at the end. */ -static int cbfs_extend_hash_master_header(struct vb2_digest_context *ctx, - const struct region_device *cbfs) -{ - struct region_device rdev; - int rv; - - if (rdev_chain(&rdev, cbfs, 0, sizeof(struct cbfs_header))) - return VB2_ERROR_UNKNOWN; - - rv = cbfs_extend_hash_with_offset(ctx, cbfs, &rdev); - - if (rv) - return rv; - - /* Include potential relative offset at end of region. */ - if (rdev_chain(&rdev, cbfs, region_device_sz(cbfs) - sizeof(int32_t), - sizeof(int32_t))) - return VB2_ERROR_UNKNOWN; - - return cbfs_extend_hash_with_offset(ctx, cbfs, &rdev); -} - -int cbfs_vb2_hash_contents(const struct region_device *cbfs, - enum vb2_hash_algorithm hash_alg, void *digest, - size_t digest_sz) -{ - struct vb2_digest_context ctx; - int rv; - struct cbfsf f; - struct cbfsf *prev; - struct cbfsf *fh; - - rv = vb2_digest_init(&ctx, hash_alg); - - if (rv) - return rv; - - rv = cbfs_extend_hash_master_header(&ctx, cbfs); - if (rv) - return rv; - - prev = NULL; - fh = &f; - - while (1) { - uint32_t ftype; - - rv = cbfs_for_each_file(cbfs, prev, fh); - prev = fh; - - if (rv < 0) - return VB2_ERROR_UNKNOWN; - - /* End of CBFS. */ - if (rv > 0) - break; - - rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->metadata); - - if (rv) - return rv; - - /* Include data contents in hash if file is non-empty. */ - if (cbfsf_file_type(fh, &ftype)) - return VB2_ERROR_UNKNOWN; - - if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_NULL) - continue; - - rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->data); - - if (rv) - return rv; - } - - return vb2_digest_finalize(&ctx, digest, digest_sz); -} diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h deleted file mode 100644 index 6565c1d..0000000 --- a/src/commonlib/include/commonlib/cbfs.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _COMMONLIB_CBFS_H_ -#define _COMMONLIB_CBFS_H_ - -#include <commonlib/bsd/cbfs_private.h> -#include <commonlib/region.h> -#include <vb2_api.h> - -/* Object representing cbfs files. */ -struct cbfsf { - struct region_device metadata; - struct region_device data; - union cbfs_mdata mdata; -}; - -/* Locate file by name and optional type. Returns 0 on success else < 0 on - * error.*/ -int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, - const char *name, uint32_t *type); - -static inline void cbfs_file_data(struct region_device *data, - const struct cbfsf *file) -{ - rdev_chain_full(data, &file->data); -} - -static inline void cbfs_file_metadata(struct region_device *metadata, - const struct cbfsf *file) -{ - rdev_chain_full(metadata, &file->metadata); -} - -/* - * Provide a handle to each cbfs file within a cbfs. The prev pointer represents - * the previous file (NULL on first invocation). The next object gets filled - * out with the next file. This returns < 0 on error, 0 on finding the next - * file, and > 0 at end of cbfs. - */ -int cbfs_for_each_file(const struct region_device *cbfs, - const struct cbfsf *prev, struct cbfsf *fh); - -/* - * Return the offset for each CBFS attribute in a CBFS file metadata region. - * The metadata must already be fully mapped by the caller. Will return the - * offset (relative to the start of the metadata) or 0 when there are no - * further attributes. Should be called with 0 to begin, then always with - * the previously returned value until it returns 0. - */ -size_t cbfs_for_each_attr(void *metadata, size_t metadata_size, - size_t last_offset); - -/* - * Find out the decompression algorithm and decompressed size of a non-stage - * CBFS file (by parsing its metadata attributes), and return them with - * out-parameters. Returns 0 on success and < 0 on error. - */ -int cbfsf_decompression_info(struct cbfsf *fh, uint32_t *algo, size_t *size); - -/* - * Return the CBFS file type as out-parameter. - * Returns 0 on success and < 0 on error. - */ -int cbfsf_file_type(struct cbfsf *fh, uint32_t *ftype); - -/* - * Perform the vb2 hash over the CBFS region skipping empty file contents. - * Caller is responsible for providing the hash algorithm as well as storage - * for the final digest. Return 0 on success or non-zero on error. - */ -int cbfs_vb2_hash_contents(const struct region_device *cbfs, - enum vb2_hash_algorithm hash_alg, void *digest, - size_t digest_sz); - -#endif diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 6c79625..5731d6e 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -5,9 +5,9 @@ #include <cbmem.h> #include <commonlib/bsd/cbfs_mdata.h> -#include <commonlib/cbfs.h> #include <commonlib/mem_pool.h> #include <commonlib/region.h> +#include <endian.h> #include <program_loading.h> #include <types.h> #include <vb2_sha.h> @@ -190,16 +190,6 @@ /********************************************************************************************** - * LEGACY APIs, TO BE DEPRECATED/REPLACED * - **********************************************************************************************/ - -/* Locate file by name and optional type. Return 0 on success. < 0 on error. */ -int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type); -/* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ -int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, - const char *name, uint32_t *type); - -/********************************************************************************************** * INTERNAL HELPERS FOR INLINES, DO NOT USE. * **********************************************************************************************/ cb_err_t _cbfs_boot_lookup(const char *name, bool force_ro, diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 0b58913..991c9fe 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -6,7 +6,6 @@ #include <cbmem.h> #include <commonlib/bsd/cbfs_private.h> #include <commonlib/bsd/compression.h> -#include <commonlib/endian.h> #include <console/console.h> #include <fmap.h> #include <lib.h> @@ -84,25 +83,6 @@ return CB_SUCCESS; } -int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) -{ - if (_cbfs_boot_lookup(name, false, &fh->mdata, &fh->data)) - return -1; - - size_t msize = be32toh(fh->mdata.h.offset); - if (rdev_chain_mem(&fh->metadata, &fh->mdata, msize)) - return -1; - - if (type) { - if (!*type) - *type = be32toh(fh->mdata.h.type); - else if (*type != be32toh(fh->mdata.h.type)) - return -1; - } - - return 0; -} - void cbfs_unmap(void *mapping) { /* @@ -115,26 +95,6 @@ mem_pool_free(&cbfs_cache, mapping); } -int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, - const char *name, uint32_t *type) -{ - struct region_device rdev; - int ret = 0; - if (fmap_locate_area_as_rdev(region_name, &rdev)) { - LOG("%s region not found while looking for %s\n", region_name, name); - return -1; - } - - uint32_t dummy_type = 0; - if (!type) - type = &dummy_type; - - ret = cbfs_locate(fh, &rdev, name, type); - /* No more measuring here, this function will be removed next patch. */ - - return ret; -} - static inline bool fsps_env(void) { /* FSP-S is assumed to be loaded in ramstage. */ diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index 8ebb661..c4d051d 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -3,7 +3,6 @@ #ifndef __SECURITY_TSPI_CRTM_H__ #define __SECURITY_TSPI_CRTM_H__ -#include <commonlib/cbfs.h> #include <program_loading.h> #include <security/tpm/tspi.h> #include <types.h> diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 26f2484..3e29c7e 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -251,8 +251,8 @@ default n depends on VBOOT_SLOTS_RW_A help - When this option is enabled cbfs_boot_locate will look for a file in the RO - (COREBOOT) region if it isn't available in the active RW region. + When this option is enabled, the CBFS code will look for a file in the + RO (COREBOOT) region if it isn't available in the active RW region. config VBOOT_EARLY_EC_SYNC bool diff --git a/tests/lib/cbfs-lookup-test.c b/tests/lib/cbfs-lookup-test.c index 27abca3..78481d7 100644 --- a/tests/lib/cbfs-lookup-test.c +++ b/tests/lib/cbfs-lookup-test.c @@ -3,6 +3,7 @@ #include <assert.h> #include <cbfs.h> #include <commonlib/bsd/cbfs_mdata.h> +#include <commonlib/bsd/cbfs_private.h> #include <commonlib/region.h> #include <string.h> #include <tests/lib/cbfs_util.h> diff --git a/tests/lib/cbfs-verification-test.c b/tests/lib/cbfs-verification-test.c index 3f35739..1f46c7d 100644 --- a/tests/lib/cbfs-verification-test.c +++ b/tests/lib/cbfs-verification-test.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbfs.h> +#include <commonlib/bsd/cbfs_private.h> #include <commonlib/region.h> #include <string.h> #include <tests/lib/cbfs_util.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/59682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Gerrit-Change-Number: 59682 Gerrit-PatchSet: 5 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2021