coreboot-gerrit December 2021

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Change in coreboot[master]: libpayload/Makefile: Improve object files list creation
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

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Change in coreboot[master]: libpayload/Makefile: Improve object files list creation
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Jakub Czapiga, Julius Werner, Jan Dabros. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59843 ) Change subject: libpayload/Makefile: Improve object files list creation ...................................................................... Patch Set 2: (1 comment) File payloads/libpayload/Makefile: https://review.coreboot.org/c/coreboot/+/59843/comment/f1de06b8_3c39f512 PS1, Line 322: # $1 lib name > Are you sure, we should change it? coreboot has stages after all, and libpayload does have libs. […] It's also called "class" in line 329 here. The advantage of sticking to the generic name would be that we could synchronize the two copies every now and then. On the other hand: maybe they already diverged enough to be separate entities by now, not sure. In any case, as mentioned that would be a follow up, so resolving this. -- To view, visit https://review.coreboot.org/c/coreboot/+/59843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1280c0a3f7e99aad2ecf8a0379a98af31ccefc3 Gerrit-Change-Number: 59843 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 15:38:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: update DRAM ID table for all variants
by Chris Wang (Code Review) 06 Dec '21

06 Dec '21

Chris Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59920 ) Change subject: mb/google/guybrush: update DRAM ID table for all variants ...................................................................... mb/google/guybrush: update DRAM ID table for all variants We use the fixed DRAM strap pin for APCB and it crosses all guybrush variants. This change will move all the mem_parts_used.txt to baseboard and use the unify mem_parts_used.txt for all variants to avoid people being confused. BUG=b:203014978 BRANCH=none TEST=emerge-guybrush coreboot chromeos-bootimage and boot to dewatt successfully Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I9cc21f1a032e97cf30d7eb072bbf6894c01e8bbc --- R src/mainboard/google/guybrush/variants/baseboard/memory/Makefile.inc R src/mainboard/google/guybrush/variants/baseboard/memory/dram_id.generated.txt R src/mainboard/google/guybrush/variants/baseboard/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/dewatt/Makefile.inc D src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc D src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt D src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/guybrush/Makefile.inc D src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc D src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt D src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc 12 files changed, 12 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/59920/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc21f1a032e97cf30d7eb072bbf6894c01e8bbc Gerrit-Change-Number: 59920 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: update DRAM ID table for all variants
by Chris Wang (Code Review) 06 Dec '21

06 Dec '21

Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59920 ) Change subject: mb/google/guybrush: update DRAM ID table for all variants ...................................................................... mb/google/guybrush: update DRAM ID table for all variants We use the fixed DRAM strap pin for APCB and it crosses all guybrush variants. This change will move all the mem_parts_used.txt to baseboard and use the unify mem_parts_used.txt for all variants to avoid people being confused. BUG=b:203014978 BRANCH=none TEST=emerge-guybrush coreboot chromeos-bootimage and boot to dewatt successfully Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I9cc21f1a032e97cf30d7eb072bbf6894c01e8bbc --- M src/mainboard/google/guybrush/variants/dewatt/Makefile.inc D src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc D src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt D src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/guybrush/Makefile.inc D src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc D src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt D src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc D src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc D src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt D src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt 12 files changed, 3 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/59920/1 diff --git a/src/mainboard/google/guybrush/variants/dewatt/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/Makefile.inc index 88e75bd..f840dfa 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/dewatt/Makefile.inc @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-or-later -subdirs-y += ./memory +subdirs-y += ../baseboard/memory diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc deleted file mode 100644 index 069b2eb..0000000 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt - -SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt deleted file mode 100644 index 5ce9e79..0000000 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt - -DRAM Part Name ID to assign -K4U6E3S4AB-MGCL 0 (0000) -H54G46CYRBX267 0 (0000) -MT53E1G32D2NP-046 WT:B 1 (0001) -MT53E512M32D1NP-046 WT:B 0 (0000) diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt deleted file mode 100644 index 4b6ba22..0000000 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt +++ /dev/null @@ -1,4 +0,0 @@ -K4U6E3S4AB-MGCL -H54G46CYRBX267 -MT53E1G32D2NP-046 WT:B -MT53E512M32D1NP-046 WT:B diff --git a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc index fa2c4de..801e350 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc @@ -11,6 +11,6 @@ verstage-y += gpio.c -subdirs-y += ./memory +subdirs-y += ../baseboard/memory smm-y += gpio.c diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc deleted file mode 100644 index 5af83ad..0000000 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/guybrush/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt - -SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE -SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt deleted file mode 100644 index 02c1bf3..0000000 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/guybrush/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt - -DRAM Part Name ID to assign -MT53E1G32D2NP-046 WT:A 0 (0000) -MT53E512M32D2NP-046 WT:F 1 (0001) -NT6AP256T32AV-J1 2 (0010) -H9HCNNNBKMMLXR-NEE 1 (0001) -MT53E1G32D2NP-046 WT:B 3 (0011) diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt deleted file mode 100644 index b267e53..0000000 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt +++ /dev/null @@ -1,5 +0,0 @@ -MT53E1G32D2NP-046 WT:A -MT53E512M32D2NP-046 WT:F -NT6AP256T32AV-J1 -H9HCNNNBKMMLXR-NEE -MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc index d7ec6dd..f6a771b 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc @@ -11,6 +11,6 @@ ramstage-y += ramstage.c -subdirs-y += ./memory +subdirs-y += ../baseboard/memory smm-y += gpio.c diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc deleted file mode 100644 index b2a552c..0000000 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt - -SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR -SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt deleted file mode 100644 index af5e980..0000000 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt - -DRAM Part Name ID to assign -MT53E1G32D2NP-046 WT:A 0 (0000) -MT53E512M32D2NP-046 WT:F 1 (0001) -NT6AP256T32AV-J1 2 (0010) -H9HCNNNBKMMLXR-NEE 1 (0001) -MT53E1G32D2NP-046 WT:B 3 (0011) -MT53E512M32D2NP-046 WT:E 1 (0001) -K4U6E3S4AA-MGCR 1 (0001) -H9HCNNNCPMMLXR-NEE 3 (0011) -K4UBE3D4AA-MGCR 3 (0011) diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt deleted file mode 100644 index eb702a6..0000000 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt +++ /dev/null @@ -1,9 +0,0 @@ -MT53E1G32D2NP-046 WT:A -MT53E512M32D2NP-046 WT:F -NT6AP256T32AV-J1 -H9HCNNNBKMMLXR-NEE -MT53E1G32D2NP-046 WT:B -MT53E512M32D2NP-046 WT:E -K4U6E3S4AA-MGCR -H9HCNNNCPMMLXR-NEE -K4UBE3D4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/59920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc21f1a032e97cf30d7eb072bbf6894c01e8bbc Gerrit-Change-Number: 59920 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Google/Nipperkin: Add board specific value for eDP tunning
by Bao Zheng (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59919 to review the following change. Change subject: Google/Nipperkin: Add board specific value for eDP tunning ...................................................................... Google/Nipperkin: Add board specific value for eDP tunning BUG=b:203061533 Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/59919/1 diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 2d3b162..6cc7bba 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -92,6 +92,19 @@ .early_init = true, }" + register "edp_phy_override" = "1" + + #bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2, bit3=1: DP3 + register "edp_physel" = "0x1" + + register "edp_tuningset" = "{ + .dp_vs_pemph_level = 0x00, + .tx_eq_main = 0x1F, + .tx_eq_pre = 0x0, + .tx_eq_post = 0x0, + .tx_vboost_lvl = 0x5, + }" + device ref i2c_0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/59919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Gerrit-Change-Number: 59919 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: Cezanne FSP wrapper: Add UPD entry for eDP tunning
by Bao Zheng (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59918 to review the following change. Change subject: Cezanne FSP wrapper: Add UPD entry for eDP tunning ...................................................................... Cezanne FSP wrapper: Add UPD entry for eDP tunning BUG=b:203061533 Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 3 files changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59918/1 diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 850d1bb..8ae62a5 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -105,6 +105,19 @@ uint8_t usb_phy_custom; struct usb_phy_config usb_phy; + + /* eDP phy tuning settings */ + uint8_t edp_phy_override; + /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */ + uint8_t edp_physel; + + struct { + uint8_t dp_vs_pemph_level; + uint8_t tx_eq_main; + uint8_t tx_eq_pre; + uint8_t tx_eq_post; + uint8_t tx_vboost_lvl; + } edp_tuningset; }; #endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 51e04e1..92debe3 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -157,6 +157,16 @@ mcfg->usb_phy = NULL; } + if (config->edp_phy_override) { + mcfg->edp_phy_override = config->edp_phy_override; + mcfg->edp_physel = config->edp_physel; + mcfg->dp_vs_pemph_level = config->edp_tuningset.dp_vs_pemph_level; + mcfg->tx_eq_main = config->edp_tuningset.tx_eq_main; + mcfg->tx_eq_pre = config->edp_tuningset.tx_eq_pre; + mcfg->tx_eq_post = config->edp_tuningset.tx_eq_post; + mcfg->tx_vboost_lvl = config->edp_tuningset.tx_vboost_lvl; + } + fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); mb_pre_fspm(); diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index f21ca42..7cee318 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -95,7 +95,14 @@ /** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset; /** Offset 0x04D7**/ uint8_t UnusedUpdSpace1; /** Offset 0x04D8**/ struct usb_phy_config *usb_phy; - /** Offset 0x04DC**/ uint8_t UnusedUpdSpace2[292]; + /** Offset 0x04DC**/ uint8_t edp_phy_override; + /** Offset 0x04DD**/ uint8_t edp_physel; + /** Offset 0x04DE**/ uint8_t dp_vs_pemph_level; + /** Offset 0x04DF**/ uint8_t tx_eq_main; + /** Offset 0x04E0**/ uint8_t tx_eq_pre; + /** Offset 0x04E1**/ uint8_t tx_eq_post; + /** Offset 0x04E2**/ uint8_t tx_vboost_lvl; + /** Offset 0x04E3**/ uint8_t UnusedUpdSpace2[285]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/59918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Gerrit-Change-Number: 59918 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Hook up DPTF device to devicetree
by Tim Crawford (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Jeremy Soller, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59886 ) Change subject: soc/intel/tigerlake: Hook up DPTF device to devicetree ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Gerrit-Change-Number: 59886 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 15:07:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Hook up SMBus device to devicetree
by Tim Crawford (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Sean Rhodes, Jeremy Soller, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59883 ) Change subject: soc/intel/tigerlake: Hook up SMBus device to devicetree ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Gerrit-Change-Number: 59883 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 15:05:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLER
by Paul Menzel (Code Review) 06 Dec '21

06 Dec '21

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59912 ) Change subject: cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLER ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59912/comment/db02c613_bc5dc2c6 PS2, Line 16: > Done For next time, it would be great, if you added it as a separate line with a colon (:) right about the Change-Id line for example. (That’s how the Linux kernel does it.) -- To view, visit https://review.coreboot.org/c/coreboot/+/59912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4ce0dca2f29754d131dacf2da63e946be9a7b6d Gerrit-Change-Number: 59912 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 15:00:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: northbridge/amd/pi/00730F01/northbridge.c: remove unneeded global var...
by Felix Held (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Michał Kopeć. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59870 ) Change subject: northbridge/amd/pi/00730F01/northbridge.c: remove unneeded global variables ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20a47f967093ef91355377c164656cabadc30fe6 Gerrit-Change-Number: 59870 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 14:53:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021