coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/northbridge/amd/agesa/family14: Enable PARALLEL_MP
by Michał Żygowski (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Michał Kopeć. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59807 ) Change subject: src/northbridge/amd/agesa/family14: Enable PARALLEL_MP ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59807/comment/c155d5a8_7c6137db PS4, Line 11: TEST=Boot on PC Engines apu1 Missing a word what has been booted to test the patch -- To view, visit https://review.coreboot.org/c/coreboot/+/59807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39a0779bdf115eebe31290591152b920acde773e Gerrit-Change-Number: 59807 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 16:50:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/amd/pi/Kconfig: select NO_SMM
by Michał Żygowski (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Michał Kopeć. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59810 ) Change subject: cpu/amd/pi/Kconfig: select NO_SMM ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47237421c3dd5bd043447831263d72c9956cdaf4 Gerrit-Change-Number: 59810 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 16:46:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/amd/agesa/Kconfig: select NO_SMM for Family 14h
by Michał Żygowski (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Michał Kopeć. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59809 ) Change subject: cpu/amd/agesa/Kconfig: select NO_SMM for Family 14h ...................................................................... Patch Set 5: (1 comment) File src/cpu/amd/agesa/Kconfig: https://review.coreboot.org/c/coreboot/+/59809/comment/a7d724bf_9701487c PS5, Line 15: select NO_SMM if CPU_AMD_AGESA_FAMILY14 Maybe let's move those setting to the appropriate CPU Kconfig file. That way each CPU family may independently switch to NO_SMM or SMM_TSEG -- To view, visit https://review.coreboot.org/c/coreboot/+/59809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09bbe036a88dada847219606ec79c68e7ca8e5cc Gerrit-Change-Number: 59809 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 16:45:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/postcar: Use a separate stack for C execution
by Raul Rangel (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Lee Leahy, Huang Jin, Arthur Heymans, Patrick Rudolph, Aaron Durbin. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54298 ) Change subject: arch/x86/postcar: Use a separate stack for C execution ...................................................................... Patch Set 5: (1 comment) File src/arch/x86/exit_car.S: https://review.coreboot.org/c/coreboot/+/54298/comment/9959749e_ca303e8c PS5, Line 108: post_car_stack_top What's wrong with the post_car_stack? -- To view, visit https://review.coreboot.org/c/coreboot/+/54298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67cbc988051036b1a0519cec9ed614acede31fd7 Gerrit-Change-Number: 54298 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 16:44:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add ADL-P 6+8+2 (28W) VR config
by Tim Wawrzynczak (Code Review) 06 Dec '21

06 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59736 ) Change subject: soc/intel/alderlake: Add ADL-P 6+8+2 (28W) VR config ...................................................................... soc/intel/alderlake: Add ADL-P 6+8+2 (28W) VR config We only have ADL-P 6+8+2 (45W) VR configuration now. Based on the power map, fill in correct ADL-P 6+8+2 (28W) VR configuration. BUG=b:202486131 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59736 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/vr_config.c 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 8f2edf9..1964c12 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -50,9 +50,11 @@ return 0; } +/* Per the power map from #613643, update ADL-P 6+8+2 (28W) VR configuration */ static const struct vr_lookup vr_config_ll[] = { { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, @@ -61,6 +63,7 @@ static const struct vr_lookup vr_config_icc[] = { { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 50) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 50) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(111, 50) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 50) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, @@ -69,6 +72,7 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = { { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, @@ -77,6 +81,7 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, -- To view, visit https://review.coreboot.org/c/coreboot/+/59736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b Gerrit-Change-Number: 59736 Gerrit-PatchSet: 6 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add ADL-P 6+8+2 (28W) VR config
by Tim Wawrzynczak (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Paul Menzel, Curtis Chen, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59736 ) Change subject: soc/intel/alderlake: Add ADL-P 6+8+2 (28W) VR config ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b Gerrit-Change-Number: 59736 Gerrit-PatchSet: 5 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 16:39:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Improve x86_64
by Tim Wawrzynczak (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Patrick Rudolph, Paul Menzel. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56017 ) Change subject: Documentation: Improve x86_64 ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855 Gerrit-Change-Number: 56017 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 16:38:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cpu/car/exit_car_fsp.S: Align stack
by Raul Rangel (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59914 ) Change subject: soc/intel/common/block/cpu/car/exit_car_fsp.S: Align stack ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b5864cfb9b013559cd318bc01733ba4d3792e65 Gerrit-Change-Number: 59914 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 16:32:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Cezanne FSP wrapper: Add UPD entry for eDP tunning
by Raul Rangel (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Zheng Bao, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59918 ) Change subject: Cezanne FSP wrapper: Add UPD entry for eDP tunning ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/cezanne/chip.h: https://review.coreboot.org/c/coreboot/+/59918/comment/a80d1a42_de2b36ce PS1, Line 111: /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */ Does this mean you will apply the same tuning parameters to multiple DPs? -- To view, visit https://review.coreboot.org/c/coreboot/+/59918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Gerrit-Change-Number: 59918 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Dec 2021 16:30:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: update DRAM ID table for all variants
by Chris Wang (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Chris Wang. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59920 to look at the new patch set (#3). Change subject: mb/google/guybrush: update DRAM ID table for all variants ...................................................................... mb/google/guybrush: update DRAM ID table for all variants We use the fixed DRAM strap pin for APCB and it crosses all guybrush variants. This change will move all the mem_parts_used.txt to baseboard and use the unify mem_parts_used.txt for all variants to avoid people being confused. BUG=b:203014978 BRANCH=none TEST=emerge-guybrush coreboot chromeos-bootimage and boot to dewatt successfully Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I9cc21f1a032e97cf30d7eb072bbf6894c01e8bbc --- R src/mainboard/google/guybrush/variants/baseboard/memory/Makefile.inc R src/mainboard/google/guybrush/variants/baseboard/memory/dram_id.generated.txt R src/mainboard/google/guybrush/variants/baseboard/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/dewatt/Makefile.inc D src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc D src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt D src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/guybrush/Makefile.inc D src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc D src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt D src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc 12 files changed, 12 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/59920/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc21f1a032e97cf30d7eb072bbf6894c01e8bbc Gerrit-Change-Number: 59920 Gerrit-PatchSet: 3 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021