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Change in coreboot[master]: mb/google/guybrush: Combine mem_parts_used.txt
by Rob Barnes (Code Review) 06 Dec '21

06 Dec '21

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59923 ) Change subject: mb/google/guybrush: Combine mem_parts_used.txt ...................................................................... mb/google/guybrush: Combine mem_parts_used.txt Combine guybrush mem_parts_used.txt across guybrush variants. Guybrush reference memory parts is used as the base, then Nipperkin memory parts were appended, followed by DeWatt memory parts. Duplicates were removed. The memory id mapping was not affected on guybrush reference and Nipperkin. DeWatt memory id mapping was affected, DeWatt boards will need to be adjusted. This works around a limitation in APCB, which currently only supports one set of memory SPDs. BUG=b:209486790, b:204151079 BRANCH=None TEST=Boot guybrush and nipperkin Change-Id: Ie17025e092f2b9397afea33fce285e80ef5dc995 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc M src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt D src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc M src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt M src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc M src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt D src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt 9 files changed, 40 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/59923/1 diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc index 069b2eb..26f27d5 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc @@ -1,8 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt index 5ce9e79..6a7b18b 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt @@ -1,10 +1,18 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt DRAM Part Name ID to assign -K4U6E3S4AB-MGCL 0 (0000) -H54G46CYRBX267 0 (0000) -MT53E1G32D2NP-046 WT:B 1 (0001) -MT53E512M32D1NP-046 WT:B 0 (0000) +MT53E1G32D2NP-046 WT:A 0 (0000) +MT53E512M32D2NP-046 WT:F 1 (0001) +NT6AP256T32AV-J1 2 (0010) +H9HCNNNBKMMLXR-NEE 1 (0001) +MT53E1G32D2NP-046 WT:B 3 (0011) +MT53E512M32D2NP-046 WT:E 1 (0001) +K4U6E3S4AA-MGCR 1 (0001) +H9HCNNNCPMMLXR-NEE 3 (0011) +K4UBE3D4AA-MGCR 3 (0011) +K4U6E3S4AB-MGCL 1 (0001) +H54G46CYRBX267 1 (0001) +MT53E512M32D1NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt deleted file mode 100644 index 4b6ba22..0000000 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt +++ /dev/null @@ -1,4 +0,0 @@ -K4U6E3S4AB-MGCL -H54G46CYRBX267 -MT53E1G32D2NP-046 WT:B -MT53E512M32D1NP-046 WT:B diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc index 5af83ad..9c40489 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc @@ -5,6 +5,6 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt index 02c1bf3..44c16e9 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt @@ -9,3 +9,10 @@ NT6AP256T32AV-J1 2 (0010) H9HCNNNBKMMLXR-NEE 1 (0001) MT53E1G32D2NP-046 WT:B 3 (0011) +MT53E512M32D2NP-046 WT:E 1 (0001) +K4U6E3S4AA-MGCR 1 (0001) +H9HCNNNCPMMLXR-NEE 3 (0011) +K4UBE3D4AA-MGCR 3 (0011) +K4U6E3S4AB-MGCL 1 (0001) +H54G46CYRBX267 1 (0001) +MT53E512M32D1NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt index b267e53..a91017c 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt @@ -3,3 +3,10 @@ NT6AP256T32AV-J1 H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:B +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR +K4U6E3S4AB-MGCL +H54G46CYRBX267 +MT53E512M32D1NP-046 WT:B diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc index b2a552c..71e59b5 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt index af5e980..7920b43 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E1G32D2NP-046 WT:A 0 (0000) @@ -13,3 +13,6 @@ K4U6E3S4AA-MGCR 1 (0001) H9HCNNNCPMMLXR-NEE 3 (0011) K4UBE3D4AA-MGCR 3 (0011) +K4U6E3S4AB-MGCL 1 (0001) +H54G46CYRBX267 1 (0001) +MT53E512M32D1NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt deleted file mode 100644 index eb702a6..0000000 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt +++ /dev/null @@ -1,9 +0,0 @@ -MT53E1G32D2NP-046 WT:A -MT53E512M32D2NP-046 WT:F -NT6AP256T32AV-J1 -H9HCNNNBKMMLXR-NEE -MT53E1G32D2NP-046 WT:B -MT53E512M32D2NP-046 WT:E -K4U6E3S4AA-MGCR -H9HCNNNCPMMLXR-NEE -K4UBE3D4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/59923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie17025e092f2b9397afea33fce285e80ef5dc995 Gerrit-Change-Number: 59923 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Hook up SMBus device to devicetree
by Sean Rhodes (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Felix Singer, Jeremy Soller, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59883 ) Change subject: soc/intel/tigerlake: Hook up SMBus device to devicetree ...................................................................... Patch Set 7: Code-Review+1 (1 comment) Patchset: PS7: Nice. Would you mind leaving ours on though? -- To view, visit https://review.coreboot.org/c/coreboot/+/59883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Gerrit-Change-Number: 59883 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 20:27:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_init
by Raul Rangel (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59922 ) Change subject: mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_init ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: It still doesn't boot to the OS because FSP dies in FSP-M, but it's a start. -- To view, visit https://review.coreboot.org/c/coreboot/+/59922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130 Gerrit-Change-Number: 59922 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Dec 2021 19:52:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_init
by Raul Rangel (Code Review) 06 Dec '21

06 Dec '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59922 ) Change subject: mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_init ...................................................................... mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_init These functions can't be weak, because they actually need to configure the GPIOs for eSPI and the TPM. With this change zork boots again. I also noticed that zork doesn't use the early table in bootblock. This means that zork will only boot if psp_verstage is enabled. BUG=b:209465425 TEST=boot zork to ramstage Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130 --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/verstage.c M src/soc/amd/common/psp_verstage/psp_verstage.c 5 files changed, 85 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/59922/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 5d3e21f..45b9e1d 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -311,25 +311,43 @@ return gpio_sleep_table; } -static const struct soc_amd_gpio early_gpio_table[] = { - /* H1_FCH_INT_ODL */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), - /* I2C3_SCL - H1 */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA - H1 */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), +static const struct soc_amd_gpio espi_gpio_table[] = { /* PCIE_RST0_L - Fixed timings */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* FCH_ESPI_EC_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* ESPI_ALERT_L */ PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), +}; + +const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; +} + +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_11, PULL_NONE), +}; + +const __weak struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} + +static const struct soc_amd_gpio early_gpio_table[] = { /* UART0_RXD - DEBUG */ PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), /* UART0_TXD - DEBUG */ PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), - /* EC_IN_RW_OD */ - PAD_GPI(GPIO_11, PULL_NONE), }; const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 415c426..7220c38 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -360,25 +360,43 @@ return gpio_sleep_table; } -static const struct soc_amd_gpio early_gpio_table[] = { - /* H1_FCH_INT_ODL */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), - /* I2C3_SCL - H1 */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA - H1 */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), +static const struct soc_amd_gpio espi_gpio_table[] = { /* PCIE_RST0_L - Fixed timings */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* FCH_ESPI_EC_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* ESPI_ALERT_L */ PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; +} + +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_130, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} + +static const struct soc_amd_gpio early_gpio_table[] = { /* UART0_RXD - DEBUG */ PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), /* UART0_TXD - DEBUG */ PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), - /* EC_IN_RW_OD */ - PAD_GPI(GPIO_130, PULL_NONE), }; const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 3f7e5d1..38c5d4a 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -33,6 +33,12 @@ */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); +/* This function provides GPIO settings for eSPI bus. */ +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); + +/* This function provides GPIO settings for TPM i2c bus. */ +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size); + void variant_updm_update(FSP_M_CONFIG *mcfg); /* Program any required GPIOs at the finalize phase */ diff --git a/src/mainboard/google/zork/verstage.c b/src/mainboard/google/zork/verstage.c index e1277f4..0603257 100644 --- a/src/mainboard/google/zork/verstage.c +++ b/src/mainboard/google/zork/verstage.c @@ -2,6 +2,7 @@ #include <amdblocks/gpio.h> #include <baseboard/variants.h> +#include <psp_verstage.h> #include <security/vboot/vboot_common.h> static void setup_gpio(void) @@ -19,3 +20,27 @@ { setup_gpio(); } + +void verstage_mainboard_espi_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_espi_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); +} + +void verstage_mainboard_tpm_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_tpm_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); +} diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 2e3d09d..05c14d6 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -25,9 +25,6 @@ extern char _bss_start, _bss_end; -void __weak verstage_mainboard_early_init(void) {} -void __weak verstage_mainboard_espi_init(void) {} -void __weak verstage_mainboard_tpm_init(void) {} void __weak verstage_mainboard_init(void) {} uint32_t __weak get_max_workbuf_size(uint32_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/59922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130 Gerrit-Change-Number: 59922 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/cbfstool: Ensure that htole32 et al are visible when building
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59891 ) Change subject: util/cbfstool: Ensure that htole32 et al are visible when building ...................................................................... util/cbfstool: Ensure that htole32 et al are visible when building endian.h wasn't included (although it probably came in as an indirect include) but in some header sets _XOPEN_SOURCE overrides _DEFAULT_SOURCE whereas the latter is a super set of the former: We should get the same things as with _XOPEN_SOURCE (such as memccpy for which it has been defined) but also extra features like htole32. Change-Id: Iaee7495b2ae64fdc719ae0879ea95fe7df286212 Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59891 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M util/cbfstool/flashmap/fmap.c 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c index c152b0d..cb67b46 100644 --- a/util/cbfstool/flashmap/fmap.c +++ b/util/cbfstool/flashmap/fmap.c @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause or GPL-2.0-only */ -#define _XOPEN_SOURCE 700 - #include <ctype.h> +#include <endian.h> #include <stdlib.h> #include <stdio.h> #include <string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/59891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaee7495b2ae64fdc719ae0879ea95fe7df286212 Gerrit-Change-Number: 59891 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/cbfstool: Ensure that htole32 et al are visible when building
by Rob Barnes (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Patrick Georgi. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59891 ) Change subject: util/cbfstool: Ensure that htole32 et al are visible when building ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaee7495b2ae64fdc719ae0879ea95fe7df286212 Gerrit-Change-Number: 59891 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 19:34:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cse: config to enable oem key manifest
by Sridhar Siricilla (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Ravindra, Arthur Heymans, Krishna P Bhat D, Patrick Rudolph, Ravindra N. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59895 ) Change subject: soc/intel/cse: config to enable oem key manifest ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3620adb2898efc002104e0ba8b2afd219c31f230 Gerrit-Change-Number: 59895 Gerrit-PatchSet: 5 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 19:32:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update gpio override
by Nick Vaccaro (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Kevin Chiu, Tim Wawrzynczak, Wisley Chen, Shon Wang. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59305 ) Change subject: mb/google/brya/var/vell: update gpio override ...................................................................... Patch Set 15: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59305/comment/902c0f79_191f3ba8 PS15, Line 10: Update initial gpio configuration for redrix remove line 10, not applicable to this CL. Description on line 9 is sufficient. -- To view, visit https://review.coreboot.org/c/coreboot/+/59305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Gerrit-Change-Number: 59305 Gerrit-PatchSet: 15 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 19:13:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update gpio override
by Nick Vaccaro (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Kevin Chiu, Tim Wawrzynczak, Wisley Chen, Shon Wang. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59305 ) Change subject: mb/google/brya/var/vell: update gpio override ...................................................................... Patch Set 15: (3 comments) File src/mainboard/google/brya/variants/vell/gpio.c: https://review.coreboot.org/c/coreboot/+/59305/comment/06d8c4cf_91b97c7a PS15, Line 13: PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), no need for this, already set as such in brya baseboard gpio.c https://review.coreboot.org/c/coreboot/+/59305/comment/a0380a63_f985d945 PS15, Line 45: PAD_CFG_GPI(GPP_E17, NONE, DEEP), no need for this, already set as such in brya baseboard gpio.c https://review.coreboot.org/c/coreboot/+/59305/comment/061f5ce6_cd4aafb8 PS15, Line 90: PAD_CFG_NF(GPD1, NONE, DEEP, NF1), no need for this, already set as such in brya baseboard gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/59305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Gerrit-Change-Number: 59305 Gerrit-PatchSet: 15 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 19:10:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cse: config to enable oem key manifest
by Tim Wawrzynczak (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Ravindra, Sridhar Siricilla, Arthur Heymans, Krishna P Bhat D, Patrick Rudolph, Ravindra N. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59895 ) Change subject: soc/intel/cse: config to enable oem key manifest ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3620adb2898efc002104e0ba8b2afd219c31f230 Gerrit-Change-Number: 59895 Gerrit-PatchSet: 5 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 19:03:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021