coreboot-gerrit December 2021

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100
by Felix Held (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59933 ) Change subject: soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100 ...................................................................... soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100 Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for Stoneyrige also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4d32fc2084bb34ea57924bae68511c6836587790 --- M src/soc/amd/stoneyridge/southbridge.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/59933/1 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index de27ac5..63bfd83 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -242,7 +242,7 @@ (fast << SPI_FAST_SPEED_NEW_SH) | (alt << SPI_ALT_SPEED_NEW_SH) | (tpm << SPI_TPM_SPEED_NEW_SH)); - spi_write16(SPI100_ENABLE, SPI_USE_SPI100); + spi_write16(SPI100_ENABLE, SPI_USE_SPI100 | spi_read16(SPI100_ENABLE)); } static void sb_disable_4dw_burst(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/59933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d32fc2084bb34ea57924bae68511c6836587790 Gerrit-Change-Number: 59933 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/spi: fix setting SPI_USE_SPI100 in SPI100_ENABLE
by Felix Held (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59932 ) Change subject: soc/amd/common/block/spi: fix setting SPI_USE_SPI100 in SPI100_ENABLE ...................................................................... soc/amd/common/block/spi: fix setting SPI_USE_SPI100 in SPI100_ENABLE Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for both Picasso and Cezanne also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=Verified that Mandolin still boots. It didn't show any signs of possibly related instabilities before though, so this test doesn't say much. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I71c2ec1729d5cb4cdff6444b637af29caaa6f1c0 --- M src/soc/amd/common/block/spi/fch_spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/59932/1 diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index fad8cd9..5ef900c 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -74,7 +74,7 @@ static void fch_spi_set_spi100(uint8_t norm, uint8_t fast, uint8_t alt, uint8_t tpm) { spi_write16(SPI100_SPEED_CONFIG, SPI_SPEED_CFG(norm, fast, alt, tpm)); - spi_write16(SPI100_ENABLE, SPI_USE_SPI100); + spi_write16(SPI100_ENABLE, SPI_USE_SPI100 | spi_read16(SPI100_ENABLE)); } static void fch_spi_configure_4dw_burst(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/59932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71c2ec1729d5cb4cdff6444b637af29caaa6f1c0 Gerrit-Change-Number: 59932 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/include/spi: update fch_spi_early_init description
by Felix Held (Code Review) 06 Dec '21

06 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59931 ) Change subject: soc/amd/common/block/include/spi: update fch_spi_early_init description ...................................................................... soc/amd/common/block/include/spi: update fch_spi_early_init description commit 90ac882a32075b44435aa19ea664b89b79cac76e (soc/amd/common/block/ spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST) introduced a Kconfig option to enable/disable the 4DW burst support in the SPI flash data prefetcher, but missed to update the documentation above the fch_spi_early_init prototype, so update the outdated documentation now. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I07c4b0b02251da63d34a172e2636894e99845d6b --- M src/soc/amd/common/block/include/amdblocks/spi.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/59931/1 diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index 81da5dd..5c3bd0e 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -94,7 +94,7 @@ * Perform early SPI initialization: * 1. Sets SPI ROM base and enables SPI ROM * 2. Enables SPI ROM prefetching - * 3. Disables 4dw burst + * 3. Disables 4 DWORD burst if !SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST * 4. Configures SPI speed and read mode. * * This function expects SoC to include soc_amd_common_config in chip SoC config and uses -- To view, visit https://review.coreboot.org/c/coreboot/+/59931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c4b0b02251da63d34a172e2636894e99845d6b Gerrit-Change-Number: 59931 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/gimble: Configure Acoustic noise mitigation
by YH Lin (Code Review) 06 Dec '21

06 Dec '21

YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59535 ) Change subject: mb/google/brya/var/gimble: Configure Acoustic noise mitigation ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Is the change applicable to evt? If so please add to gimble4es as well. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/59535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be3d30403284b98276c837adefd91aa62c971e4 Gerrit-Change-Number: 59535 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 23:52:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume
by Raul Rangel (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59929 ) Change subject: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume ...................................................................... soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardwar… > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit (and thus passing control to OSPM). For ACPI only > platforms (where SCI_EN is always set), when transitioning from either > the mechanical off (G3) or soft-off state to the G0 working state this > register is cleared prior to entering the G0 working state. This means we don't want to clear the PM1 register on resume. By clearing it the linux kernel can't correctly increment the wake count when the power button is pressed. The AMD platforms implement the _SWS ACPI methods, but the linux kernel doesn't actually use these methods. BUG=b:172021431 TEST=suspend zork and push power button and verify power button wake_count increments. Verified other wake sources still work. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 --- M src/soc/amd/cezanne/fch.c M src/soc/amd/common/block/cpu/smm/finalize.c M src/soc/amd/picasso/fch.c M src/soc/amd/stoneyridge/romstage.c 4 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/59929/1 diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index dd19c31..8cd1212 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -199,7 +199,6 @@ acpi_pm_gpe_add_events_print_events(); gpio_add_events(); - acpi_clear_pm_gpe_status(); gpp_clk_setup(); fch_clk_output_48Mhz(); diff --git a/src/soc/amd/common/block/cpu/smm/finalize.c b/src/soc/amd/common/block/cpu/smm/finalize.c index ec975be..73b2121 100644 --- a/src/soc/amd/common/block/cpu/smm/finalize.c +++ b/src/soc/amd/common/block/cpu/smm/finalize.c @@ -41,6 +41,8 @@ finalize_cores(); if (!acpi_is_wakeup_s3()) { + acpi_clear_pm_gpe_status(); + if (CONFIG(HAVE_SMI_HANDLER)) acpi_disable_sci(); else diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 44acc81..03ba914 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -225,8 +225,6 @@ acpi_pm_gpe_add_events_print_events(); gpio_add_events(); - acpi_clear_pm_gpe_status(); - al2ahb_clock_gate(); gpp_clk_setup(); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index e316d21..c732f75 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -214,6 +214,5 @@ acpi_fill_pm_gpe_state(&state->gpe_state); acpi_pm_gpe_add_events_print_events(); } - acpi_clear_pm_gpe_status(); } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) -- To view, visit https://review.coreboot.org/c/coreboot/+/59929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Gerrit-Change-Number: 59929 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPI
by Raul Rangel (Code Review) 06 Dec '21

06 Dec '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59928 ) Change subject: soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPI ...................................................................... soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPI According to https://uefi.org/specs/ACPI/6.4/16_Waking_and_Sleeping/sleeping-states.html… > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit. This change makes sure we clear the PM/GPE blocks are cleared before enabling the SCI_EN bit. BUG=b:172021431 TEST=Boot guybrush and morphius to OS and verify suspend resume still works. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Icc6f542185dc520f8d181423961b74481c0b5506 --- M src/soc/amd/cezanne/smihandler.c M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/59928/1 diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c index 7653836..2549ef8 100644 --- a/src/soc/amd/cezanne/smihandler.c +++ b/src/soc/amd/cezanne/smihandler.c @@ -23,6 +23,7 @@ switch (cmd) { case APM_CNT_ACPI_ENABLE: + acpi_clear_pm_gpe_status(); acpi_enable_sci(); break; case APM_CNT_ACPI_DISABLE: diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index b13c6e0..f9f5fc0 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -23,6 +23,7 @@ switch (cmd) { case APM_CNT_ACPI_ENABLE: + acpi_clear_pm_gpe_status(); acpi_enable_sci(); break; case APM_CNT_ACPI_DISABLE: diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index f9c4a54..50a5111 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -21,6 +21,7 @@ switch (cmd) { case APM_CNT_ACPI_ENABLE: + acpi_clear_pm_gpe_status(); acpi_enable_sci(); break; case APM_CNT_ACPI_DISABLE: -- To view, visit https://review.coreboot.org/c/coreboot/+/59928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc6f542185dc520f8d181423961b74481c0b5506 Gerrit-Change-Number: 59928 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/gimble: Configure Acoustic noise mitigation
by Tim Wawrzynczak (Code Review) 06 Dec '21

06 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59535 ) Change subject: mb/google/brya/var/gimble: Configure Acoustic noise mitigation ...................................................................... mb/google/brya/var/gimble: Configure Acoustic noise mitigation - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 16 BUG=b:206704930 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Change-Id: I2be3d30403284b98276c837adefd91aa62c971e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59535 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/gimble/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Mark Hsieh: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 27ea5aa..4bfe124 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -34,6 +34,13 @@ register "SaGv" = "SaGv_Enabled" register "PsysPmax" = "143" register "TcssAuxOri" = "1" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_16" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_16" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be3d30403284b98276c837adefd91aa62c971e4 Gerrit-Change-Number: 59535 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/gimble: Configure Acoustic noise mitigation
by Tim Wawrzynczak (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: YH Lin, Paul Menzel, Anfernee Chen, Mark Hsieh, Zhuohao Lee, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59535 ) Change subject: mb/google/brya/var/gimble: Configure Acoustic noise mitigation ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59535/comment/f12d8610_944dd81c PS1, Line 14: without error. > Hi Tim, […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be3d30403284b98276c837adefd91aa62c971e4 Gerrit-Change-Number: 59535 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Dec 2021 23:21:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Implement function to map physical port to EC port
by Tim Wawrzynczak (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Maulik V Vaghela, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59666 ) Change subject: soc/intel/alderlake: Implement function to map physical port to EC port ...................................................................... Patch Set 14: Code-Review+2 (3 comments) Patchset: PS14: Eventually I have some thoughts about moving this into devicetree, but this will work for now thanks Maulik! 😊 File src/soc/intel/alderlake/retimer.c: https://review.coreboot.org/c/coreboot/+/59666/comment/1855dc2a_562e1a5d PS14, Line 4: #include <drivers/intel/usb4/retimer/retimer.h> nit: should include <device/device.h> for `is_dev_enabled` https://review.coreboot.org/c/coreboot/+/59666/comment/afd884c5_9c233aa4 PS14, Line 6: #include <string.h> nit: is this required? -- To view, visit https://review.coreboot.org/c/coreboot/+/59666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Gerrit-Change-Number: 59666 Gerrit-PatchSet: 14 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 23:20:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/usb4/retimer: Add function to correct EC port mapping
by Tim Wawrzynczak (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Maulik V Vaghela, Sugnan Prabhu S, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59665 ) Change subject: drivers/intel/usb4/retimer: Add function to correct EC port mapping ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e Gerrit-Change-Number: 59665 Gerrit-PatchSet: 9 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 23:17:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021