coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/brya/variants/taniks: Configure GPIOs according to schematics
by Joey Peng (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: YH Lin, Joey Peng, Tim Wawrzynczak. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59938 to look at the new patch set (#2). Change subject: mb/google/brya/variants/taniks: Configure GPIOs according to schematics ...................................................................... mb/google/brya/variants/taniks: Configure GPIOs according to schematics Update initial gpio configuration for taniks BUG=b:209492408 TEST=FW_NAME=taeko emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ic5c4ead4ad59137e1764e1226415ab6041c68aab --- A src/mainboard/google/brya/variants/taniks/Makefile.inc A src/mainboard/google/brya/variants/taniks/gpio.c 2 files changed, 213 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59938/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5c4ead4ad59137e1764e1226415ab6041c68aab Gerrit-Change-Number: 59938 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
by Usha P (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Usha P. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59937 to look at the new patch set (#3). Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N ...................................................................... mb/intel/adlrvp: Configure GPIOs for Alder Lake-N List of changes: 1. Add separate file for ADL-N GPIOs 2. Configure GPIOs as per the schematics of ADL-N RVP Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/early_gpio_n.c A src/mainboard/intel/adlrvp/gpio_n.c 3 files changed, 342 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/59937/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Gerrit-Change-Number: 59937 Gerrit-PatchSet: 3 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: acpi/acpigen, drivers/tpm: Move definition of set_package_element_op
by Lance Zhao (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Sridhar Siricilla. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59729 ) Change subject: acpi/acpigen, drivers/tpm: Move definition of set_package_element_op ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fe70a1f369c97c67bbc1717e6adc7c5f4ba5839 Gerrit-Change-Number: 59729 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 07 Dec 2021 01:39:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
by Usha P (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Usha P. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59937 to look at the new patch set (#2). Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N ...................................................................... mb/intel/adlrvp: Configure GPIOs for Alder Lake-N List of changes: 1. Add separate file for ADL-N GPIOs 2. Configure GPIOs as per the schematics of ADL-N RVP Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/early_gpio_n.c A src/mainboard/intel/adlrvp/gpio_n.c 3 files changed, 343 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/59937/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Gerrit-Change-Number: 59937 Gerrit-PatchSet: 2 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/include/acpi: Move CPPC_PACKAGE_NAME macro definition
by Lance Zhao (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Arthur Heymans, Sridhar Siricilla, Michael Niewöhner. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59358 ) Change subject: src/include/acpi: Move CPPC_PACKAGE_NAME macro definition ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic547445cdbe2b1a3efe44390bd127f577386e7fc Gerrit-Change-Number: 59358 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 07 Dec 2021 01:39:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/taniks: Configure GPIOs according to schematics
by Joey Peng (Code Review) 07 Dec '21

07 Dec '21

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59938 ) Change subject: mb/google/brya/variants/taniks: Configure GPIOs according to schematics ...................................................................... mb/google/brya/variants/taniks: Configure GPIOs according to schematics Update initial gpio configuration for taniks BUG=b:209492408 TEST=FW_NAME=taeko emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ic5c4ead4ad59137e1764e1226415ab6041c68aab --- A src/mainboard/google/brya/variants/taniks/Makefile.inc A src/mainboard/google/brya/variants/taniks/gpio.c 2 files changed, 214 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59938/1 diff --git a/src/mainboard/google/brya/variants/taniks/Makefile.inc b/src/mainboard/google/brya/variants/taniks/Makefile.inc new file mode 100644 index 0000000..7a72a26 --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c + diff --git a/src/mainboard/google/brya/variants/taniks/gpio.c b/src/mainboard/google/brya/variants/taniks/gpio.c new file mode 100644 index 0000000..aa778fc --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/gpio.c @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : SRCCLKREQ7# ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A12 : SATAXPCIE1 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A18 : DDSP_HPDB ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_B15, NONE), + + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C6 : SML1CLK ==> NC */ + PAD_NC(GPP_C6, NONE), + + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D10 : ISH_SPI_CLK ==> NC */ + PAD_NC(GPP_D10, NONE), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC(GPP_D16, NONE), + /* D17 : UART1_RXD ==> NC */ + PAD_NC(GPP_D17, NONE), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + /* E10 : THC0_SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E16 : RSVD_TP ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC(GPP_E17, NONE), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> NC */ + PAD_NC(GPP_E19, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : VNN_CTRL ==> VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : BP105_CTRL ==> PP1050_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* H15 : DDPB_CTRLCLK ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H17 : DDPB_CTRLDATA ==> NC */ + PAD_NC(GPP_H17, NONE), + /* H19 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : SNDW0_DATA ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* + * B4 : PROC_GP3 ==> SSD_PERST_L + * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. + */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5c4ead4ad59137e1764e1226415ab6041c68aab Gerrit-Change-Number: 59938 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Add Kconfig for Alder Lake-N
by Usha P (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Subrata Banik, Balaji Manigandan, Krishna P Bhat D, Usha P. Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59724 ) Change subject: mb/intel/adlrvp: Add Kconfig for Alder Lake-N ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/59724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091663590966c174f980e41a31c93c44c7add529 Gerrit-Change-Number: 59724 Gerrit-PatchSet: 4 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Tue, 07 Dec 2021 01:35:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
by build bot (Jenkins) (Code Review) 07 Dec '21

07 Dec '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59937 ) Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N ...................................................................... Patch Set 1: (34 comments) File src/mainboard/intel/adlrvp/gpio_n.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/7971b3ff_0660182f PS1, Line 9: /*ESPI_IO0_EC_R / ESPI_IO0_HDR*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/3bce52da_c3a7100c PS1, Line 10: PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/42a47f04_156bbbb1 PS1, Line 10: PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/311a0126_fa4e036c PS1, Line 11: /*ESPI_IO1_EC_R / ESPI_IO1_HDR*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/cd075286_782bf183 PS1, Line 12: PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/3b72deed_4f9d86df PS1, Line 12: PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/f809c1e8_5a353aaf PS1, Line 13: /*ESPI_IO2_EC_R / ESPI_IO2_HDR*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/2d3d7fab_5dc18907 PS1, Line 14: PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/b0992747_5eabd42a PS1, Line 14: PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/c98d7404_bef16fb2 PS1, Line 15: /*ESPI_IO3_EC_R / ESPI_IO3_HDR*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/fe9b2499_4971bc01 PS1, Line 16: PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/744660d7_a16de988 PS1, Line 16: PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/fd0fa982_73559493 PS1, Line 17: /*ESPI_CS0_EC_R_N / ESPI_CS0_HDR_N*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/164b634a_7c0a3db0 PS1, Line 18: PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/a2784a49_b88e1c18 PS1, Line 18: PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/49b5dda9_3eaafce4 PS1, Line 19: /*ESPI_ALERT0_EC_R_N / ESPI_ALERT0_HDR_N*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/6cea559c_b87c0f32 PS1, Line 20: PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/afb73454_a204578a PS1, Line 20: PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/dd2edefd_83cdf28b PS1, Line 21: /*ESPI_CLK_EC_R / ESPI_CLK_HDR*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/122da39e_12ace8af PS1, Line 22: PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/6d1c1e39_7adb55d8 PS1, Line 22: PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/07fed75c_29b8b879 PS1, Line 23: /*ESPI_RST_EC_R_N / ESPI_RST_HDR_N*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/065eb275_07462f3d PS1, Line 24: PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/e5f42732_ab59da18 PS1, Line 24: PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/5598be8b_7d2d0ac1 PS1, Line 134: PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/33e994bc_72028e23 PS1, Line 134: PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/b57ba518_414f75a3 PS1, Line 211: gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/25252736_874714d5 PS1, Line 211: gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/12b95d1a_181345c8 PS1, Line 215: CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/29899232_6c5699b3 PS1, Line 215: CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/064e40c4_f73aab49 PS1, Line 220: *num = ARRAY_SIZE(cros_gpios); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/e50249f0_bcb9ba57 PS1, Line 220: *num = ARRAY_SIZE(cros_gpios); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/75fac8d0_0b704bf4 PS1, Line 221: return cros_gpios; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135051): https://review.coreboot.org/c/coreboot/+/59937/comment/661a24c6_423009dd PS1, Line 221: return cros_gpios; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/59937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Gerrit-Change-Number: 59937 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 01:34:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
by Usha P (Code Review) 07 Dec '21

07 Dec '21

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59937 ) Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N ...................................................................... mb/intel/adlrvp: Configure GPIOs for Alder Lake-N List of changes: 1. Add separate file for ADL-N GPIOs 2. Configure GPIOs as per the schematics of ADL-N RVP Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/early_gpio_n.c A src/mainboard/intel/adlrvp/gpio_n.c 3 files changed, 343 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/59937/1 diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index 04c1645..db00c9b 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -7,6 +7,9 @@ ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_M),y) bootblock-y += early_gpio_m.c ramstage-y += gpio_m.c +else ifeq($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) +bootblock-y += early_gpio_n.c +ramstage-y += gpio_n.c else bootblock-y += early_gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/intel/adlrvp/early_gpio_n.c b/src/mainboard/intel/adlrvp/early_gpio_n.c new file mode 100644 index 0000000..3c88ca2 --- /dev/null +++ b/src/mainboard/intel/adlrvp/early_gpio_n.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* CPU PCIe VGPIO for RP0 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, DEEP, NF1), + + /* CPU PCIe vGPIO for RP1 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, DEEP, NF1), + + /* CPU PCIe vGPIO for RP2 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, DEEP, NF1), + + /* CPU PCIe vGPIO for RP3 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), +}; + +static const struct pad_config early_uart_gpio_table[] = { + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +void variant_configure_early_gpio_pads(void) +{ + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); + + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/intel/adlrvp/gpio_n.c b/src/mainboard/intel/adlrvp/gpio_n.c new file mode 100644 index 0000000..e375851 --- /dev/null +++ b/src/mainboard/intel/adlrvp/gpio_n.c @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /*ESPI_IO0_EC_R / ESPI_IO0_HDR*/ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + /*ESPI_IO1_EC_R / ESPI_IO1_HDR*/ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + /*ESPI_IO2_EC_R / ESPI_IO2_HDR*/ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + /*ESPI_IO3_EC_R / ESPI_IO3_HDR*/ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + /*ESPI_CS0_EC_R_N / ESPI_CS0_HDR_N*/ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + /*ESPI_ALERT0_EC_R_N / ESPI_ALERT0_HDR_N*/ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + /*ESPI_CLK_EC_R / ESPI_CLK_HDR*/ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /*ESPI_RST_EC_R_N / ESPI_RST_HDR_N*/ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /*EC_SLP_S0_CS_N*/ + PAD_CFG_GPO(GPP_E4, 1, PLTRST), + + /*GPPC_E7_EC_SMI_N*/ + PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), + + /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* M.2_SSD_PDET_R */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /*CLKREQ0_M2_SSD_N*/ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* M2_PCH_SSD_PWREN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /*M2_SSD_RST_N */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /*M2_SSD_DEVSLP*/ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5), + + /*TYPEA_CONN23_USB2_P8_OC1_N*/ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /*CRD1_PWREN*/ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /*TCP1_DISP_AUX_P_BIAS_GPIO*/ + PAD_CFG_GPO(GPP_E20, 1, PLTRST), + /*TCP1_DISP_AUX_N_BIAS_GPIO*/ + PAD_CFG_GPO(GPP_E21, 0, PLTRST), + /*TCP0_DISP_AUX_P_BIAS_GPIO*/ + PAD_CFG_GPO(GPP_E22, 0, PLTRST), + /*TCP0_DISP_AUX_N_BIAS_GPIO*/ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + + /*EDP1_HPD_MIPI_PNL_RST*/ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /*X1_SLOT_PWREN*/ + PAD_CFG_GPO(GPP_A8, 0, PLTRST), + /*SML0_CLK*/ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /*SML0_DATA*/ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /*CLKREQ3_X1PCIE_SLOT_N*/ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /*X1_PCIE_SLOT_WAKE_N*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_D11, NONE, DEEP, LEVEL, INVERT), + /*X1_Slot_RESET*/ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + + /*WWAN_PERST_N*/ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /*CLKREQ1_WWAN_N*/ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /*GPPC_D15_M.2_WWAN_DISABLE_N*/ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /*WWAN_PWREN*/ + PAD_CFG_GPO(GPP_D17, 1, PLTRST), + /* WWAN WAKE N*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), //TODO SCI + /* SRCCLK_OEB6 */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF3), + /*GPPC_F6_CNV_PA_BLANKING*/ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 1, PLTRST), + /*WWAN_FCP_OFF_N*/ + PAD_CFG_GPO(GPP_F15, 1, PLTRST), + /*CNV_MFUART2_RXD*/ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /*CNV_MFUART2_RXD*/ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + + /*PM_SLP_S0_N*/ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /*PLT_RST_N*/ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /*PM_SLP_DRAM_N*/ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), + /*CPU_C10_GATE_N_R*/ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /*CODEC_INT_N*/ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), + /*SNDW0_CLK_HDR*/ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /*SNDW0_DATA_HDR*/ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /*SNDW1_CLK_DMIC_CLK_A_0*/ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /*SNDW1_DATA_DMIC_DATA_0*/ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /*SNDW2_CLK_R*/ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /*SNDW2_DATA_R*/ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /*SOC_DMIC0_SNDW3_CLK*/ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /*SOC_DMIC0_SNDW3_DATA*/ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* I2C_SCL(0) */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* I2C_SDA(0) */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + + /*DDIB_DP_HDMI_ALS_HDP*/ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* 8 : M.2_BTWIFI_SUS_CLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* 9 : GPD_9_SLP_WLAN_N */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + + /* SRCCLK_OEB7 */ + PAD_CFG_GPO(GPP_A7, 0, PLTRST), + + /* GPIO pin for PCIE SRCCLKREQB_2 */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + + + /* H2 : WLAN_RST_N */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* I2C_SDA(1) */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SCL(1) */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* CAM_PRIVACY_LED */ + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + + + /* B16 : I2C5 SDA */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* B17 : I2C5 SCL */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + + + /* CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), + + /* IMGCLKOUT */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + + /* D13 : WIFI_WAKE_N */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* WIFI RF KILL */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + + /* F0 : CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP_BT_UART2_RXD */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + /* F2 : CNV_RGI_DT_BT_UART2_TXD */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + /* F4 : CNV_RF_RESET_R_N */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ_R */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* TCH PAD Power EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + + /* UART_BT_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT), +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/59937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Gerrit-Change-Number: 59937 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: enable gpio locking
by 9elements QA (Code Review) 07 Dec '21

07 Dec '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58352 ) Change subject: soc/intel/alderlake: enable gpio locking ...................................................................... Patch Set 15: Automatic boot test returned (PASS/FAIL/TOTAL): 7 / 1 / 8 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/83690 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/83689 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83688 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/83687 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83686 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/83685 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/83684 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/83683 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/58352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Gerrit-Change-Number: 58352 Gerrit-PatchSet: 15 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 01:20:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021