coreboot-gerrit December 2021

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Change in coreboot[master]: soc/amd: use KiB and MiB definitions
by Felix Singer (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59936 ) Change subject: soc/amd: use KiB and MiB definitions ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56c380190b11aa3214cce31b82974327e3d15000 Gerrit-Change-Number: 59936 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Dec 2021 01:15:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3
by Cliff Huang (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59855 ) Change subject: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3 ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/pcie/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/59855/comment/79d7e77e_88a7eab7 PS2, Line 99: static void pcie_rtd3_enable_modphy_pg(unsigned int pcie_rp) Can we merge these two functions by introducing a bool arg for on/off? -- To view, visit https://review.coreboot.org/c/coreboot/+/59855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d Gerrit-Change-Number: 59855 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 00:33:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3
by Cliff Huang (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59855 ) Change subject: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3 ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/pcie/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/59855/comment/f40616b8_b40c6552 PS2, Line 39: #define PCH_PCIE_CFG_LCAP_PN 0x4f /* Root Port Number */ > Can we take this chance to clarify LCAP address? It should be 0x4C according to PCH EDS vol2 spec. I take this back, LCAP is 0x4c and the last byte is for port number (PN). -- To view, visit https://review.coreboot.org/c/coreboot/+/59855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d Gerrit-Change-Number: 59855 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 00:18:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: use KiB and MiB definitions
by Felix Held (Code Review) 07 Dec '21

07 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59936 ) Change subject: soc/amd: use KiB and MiB definitions ...................................................................... soc/amd: use KiB and MiB definitions Use KiB and MiB instead of multiplying/dividing with/by the numeric value when doing region size calculations. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I56c380190b11aa3214cce31b82974327e3d15000 --- M src/soc/amd/common/block/iommu/iommu.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/picasso/agesa_acpi.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/59936/1 diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index b6e4ac2..8628096 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -14,7 +14,7 @@ /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, 0x44); - res->size = 512 * 1024; + res->size = 512 * KiB; res->align = log2(res->size); res->gran = log2(res->size); res->limit = 0xffffffff; /* 4G */ diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 7c46645..ebded6b 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -106,7 +106,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* Add a memory resource for the SPI BAR. */ - fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, + fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / KiB, 1, IORESOURCE_SUBTRACTIVE); res = new_resource(dev, 3); /* IOAPIC */ diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 7826007..4ab31e5 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -82,7 +82,7 @@ if (memory_base == 0) { current = create_crat_memory_entry(0, 0ull, 0xa0000ull, current); - memory_base = (1 * 1024 * 1024); + memory_base = 1 * MiB; memory_length = memory_base; new_entries++; } -- To view, visit https://review.coreboot.org/c/coreboot/+/59936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56c380190b11aa3214cce31b82974327e3d15000 Gerrit-Change-Number: 59936 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: add list of gpios to lock
by Nick Vaccaro (Code Review) 07 Dec '21

07 Dec '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58353 ) Change subject: mb/google/brya: add list of gpios to lock ...................................................................... mb/google/brya: add list of gpios to lock Add a list of gpios to lock for brya. This currently includes GPIOs connected to the FPMCU. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Change-Id: Idea42a58575c280be0770d38f934acdf5508c45d Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58353 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index a28f873..0583930 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -456,3 +456,21 @@ *num = 0; return NULL; } + +static struct gpio_lock_config lockable_brya_gpios[] = { + { GPP_B6, GPIO_LOCK_CONFIG }, /* PCH_I2C_TPM_SCL */ + { GPP_B7, GPIO_LOCK_CONFIG }, /* PCH_I2C_TPM_SDA */ + { GPP_A13, GPIO_LOCK_CONFIG }, /* GSC_PCH_INT_ODL */ + { GPP_E15, GPIO_LOCK_CONFIG }, /* PCH_WP_OD */ + { GPP_F11, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CLK_FPMCU_R */ + { GPP_F13, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D1_FPMCU_D0 */ + { GPP_F12, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D0_FPMCU_D1_R */ + { GPP_F15, GPIO_LOCK_CONFIG }, /* FPMCU_INT_L */ + { GPP_F16, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CS_FPMCU_R_L */ +}; + +const struct gpio_lock_config *mb_gpio_lock_config(size_t *num) +{ + *num = ARRAY_SIZE(lockable_brya_gpios); + return lockable_brya_gpios; +} 15 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idea42a58575c280be0770d38f934acdf5508c45d Gerrit-Change-Number: 58353 Gerrit-PatchSet: 17 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: enable gpio locking
by Nick Vaccaro (Code Review) 07 Dec '21

07 Dec '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58352 ) Change subject: soc/intel/alderlake: enable gpio locking ...................................................................... soc/intel/alderlake: enable gpio locking This change supplies a list of ADL gpios that are connected to non-host (x86) controllers and should be locked after initial configuration. Set SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS to enable GPIO locking. BUG=b:210430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58352 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/gpio.c 2 files changed, 58 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 9fe2668..89570b1 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -82,6 +82,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC select SOC_INTEL_COMMON_BLOCK_USB4 diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index 8275241..aa05136e 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -247,3 +247,60 @@ *num = ARRAY_SIZE(routes); return routes; }; + +/* GPIOs controllable by non-host (x86) agent, eg. ISH, THC, etc */ +static const struct gpio_lock_config gpios_to_lock[] = { + { GPP_A16, GPIO_LOCK_CONFIG }, /* ISH_GP5 NF4 */ + { GPP_B3, GPIO_LOCK_CONFIG }, /* ISH_GP4B NF4 (not avail in ADL PCH-M) */ + { GPP_B4, GPIO_LOCK_CONFIG }, /* ISH_GP5B NF4 (not avail in ADL PCH-M) */ + { GPP_B5, GPIO_LOCK_CONFIG }, /* ISH_I2C0_SDA NF1 */ + { GPP_B6, GPIO_LOCK_CONFIG }, /* ISH_I2C0_SCL NF1 */ + { GPP_B7, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SDA NF1 */ + { GPP_B8, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SCL NF1 */ + { GPP_B14, GPIO_LOCK_CONFIG }, /* ISH_GP6 NF5 */ + { GPP_B15, GPIO_LOCK_CONFIG }, /* ISH_GP7 NF5 */ + { GPP_B16, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SDA NF4 */ + { GPP_B17, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SCL NF4 */ + { GPP_D0, GPIO_LOCK_CONFIG }, /* ISH_GP0 NF1 */ + { GPP_D1, GPIO_LOCK_CONFIG }, /* ISH_GP1 NF1 */ + { GPP_D2, GPIO_LOCK_CONFIG }, /* ISH_GP2 NF1 */ + { GPP_D3, GPIO_LOCK_CONFIG }, /* ISH_GP3 NF1 */ + { GPP_D9, GPIO_LOCK_CONFIG }, /* ISH_SPI_CS# NF1 */ + { GPP_D10, GPIO_LOCK_CONFIG }, /* ISH_SPI_CLK NF1 */ + { GPP_D11, GPIO_LOCK_CONFIG }, /* ISH_SPI_MISO NF1 */ + { GPP_D12, GPIO_LOCK_CONFIG }, /* ISH_SPI_MOSI NF1 */ + { GPP_D13, GPIO_LOCK_CONFIG }, /* ISH_UART0_RXD NF1 */ + { GPP_D14, GPIO_LOCK_CONFIG }, /* ISH_UART0_TXD NF1 */ + { GPP_D15, GPIO_LOCK_CONFIG }, /* ISH_UART0_RTS# NF1 */ + { GPP_D16, GPIO_LOCK_CONFIG }, /* ISH_UART0_CTS# NF1 */ + { GPP_D17, GPIO_LOCK_CONFIG }, /* ISH_UART1_RXD NF2 */ + { GPP_D18, GPIO_LOCK_CONFIG }, /* ISH_UART1_TXD NF2 */ + { GPP_E9, GPIO_LOCK_CONFIG }, /* ISH_GP4 NF2 */ + { GPP_H12, GPIO_LOCK_CONFIG }, /* ISH_GP6B NF4 */ + { GPP_H13, GPIO_LOCK_CONFIG }, /* ISH_GP7B NF4 */ + + { GPP_E1, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO2 NF2 */ + { GPP_E2, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO3 NF2 */ + { GPP_E6, GPIO_LOCK_CONFIG }, /* THC0_SPI1_RST# NF2 */ + { GPP_E10, GPIO_LOCK_CONFIG }, /* THC0_SPI1_CS# NF2 */ + { GPP_E11, GPIO_LOCK_CONFIG }, /* THC0_SPI1_CLK NF2 */ + { GPP_E12, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO1 NF2 */ + { GPP_E13, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO0 NF2 */ + { GPP_E17, GPIO_LOCK_CONFIG }, /* THC0_SPI1_INT# NF2 */ + { GPP_F11, GPIO_LOCK_CONFIG }, /* THC1_SPI2_CLK NF3 */ + { GPP_F12, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO0 NF3 */ + { GPP_F13, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO1 NF3 */ + { GPP_F14, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO2 NF3 */ + { GPP_F15, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO3 NF3 */ + { GPP_F16, GPIO_LOCK_CONFIG }, /* THC1_SPI2_CS# NF3 */ + { GPP_F17, GPIO_LOCK_CONFIG }, /* THC1_SPI2_RST# NF3 */ + { GPP_F18, GPIO_LOCK_CONFIG }, /* THC1_SPI2_INT# NF3 */ + + { GPP_H3, GPIO_LOCK_CONFIG }, /* SX_EXIT_HOLDOFF# NF1 */ +}; + +const struct gpio_lock_config *soc_gpio_lock_config(size_t *num) +{ + *num = ARRAY_SIZE(gpios_to_lock); + return gpios_to_lock; +} 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Gerrit-Change-Number: 58352 Gerrit-PatchSet: 15 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: add generic gpio lock mechanism
by Nick Vaccaro (Code Review) 07 Dec '21

07 Dec '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58351 ) Change subject: soc/intel/common: add generic gpio lock mechanism ...................................................................... soc/intel/common: add generic gpio lock mechanism For added security, there are some gpios that an SoC will want to lock once initially configured, such as gpios attached to non-host (x86) controllers, so that they can't be recofigured at a later point in time by rogue code. Likewise, a mainboard may have some gpios connected to secure busses and/or devices that they want to protect from being changed post initial configuration. This change adds a generic gpio locking mechanism that allows the SoC to export a list of GPIOs to be locked down and allows the mainboard to export a list of GPIOs that it wants locked down once initialization is complete. Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to enable this feature. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify brya0 boots successfully to kernel. Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58351 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/common/block/smm/smihandler.c 4 files changed, 154 insertions(+), 40 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index d4a312b..ce23a2e 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -447,14 +447,27 @@ return !!(reg & PAD_CFG0_RX_STATE); } -int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action action) +static int sideband_msg_err(int status, int response) { - const struct pad_community *comm = gpio_get_community(pad); - size_t rel_pad; - uint16_t offset; - uint32_t data; + if (status || response) { + printk(BIOS_ERR, "%s: error status=%x response=%x\n", + __func__, status, response); + return (status == -1) ? -1 : response; + } + + return 0; +} + +int gpio_lock_pads(const struct gpio_lock_config *pad_list, const size_t count) +{ + const struct pad_community *comm; + enum gpio_lock_action action; + int status, err_response = 0; uint8_t response; - int status; + uint16_t offset; + size_t rel_pad; + uint32_t data; + gpio_t pad; /* * FSP-S will unlock all the GPIO pads and hide the P2SB device. With @@ -468,23 +481,13 @@ return -1; } - if (!(action & GPIO_LOCK_FULL)) { - printk(BIOS_ERR, "%s: Error: no action specified!\n", __func__); + if ((pad_list == NULL) || (count == 0)) { + printk(BIOS_ERR, "%s: Error: pad_list null or count = 0!\n", __func__); return -1; } - rel_pad = relative_pad_in_comm(comm, pad); - offset = comm->pad_cfg_lock_offset; - if (!offset) { - printk(BIOS_ERR, "%s: Error: offset is not defined!\n", __func__); - return -1; - } - offset += gpio_group_index_scaled(comm, rel_pad, 2 * sizeof(uint32_t)); - /* We must use the sideband interface in order to lock the pad. */ struct pcr_sbi_msg msg = { - .pid = comm->port, - .offset = offset, .opcode = GPIO_LOCK_UNLOCK, .is_posted = false, .fast_byte_enable = 0xF, @@ -494,35 +497,69 @@ p2sb_unhide(); - data = gpio_bitmask_within_group(comm, rel_pad); + for (int x = 0; x < count; x++) { + int err; - if (action & GPIO_LOCK_CONFIG) { - printk(BIOS_INFO, "%s: Locking pad %d configuration\n", - __func__, pad); - status = pcr_execute_sideband_msg(&msg, &data, &response); - if (status || response) { - printk(BIOS_ERR, "%s: error status=%x response=%x\n", __func__, status, - response); - p2sb_hide(); - return status == -1 ? -1 : response; + pad = pad_list[x].gpio; + action = pad_list[x].action; + + if (!(action & GPIO_LOCK_FULL)) { + printk(BIOS_ERR, "%s: Error: no action specified for pad %d!\n", + __func__, pad); + continue; } - } - if (action & GPIO_LOCK_TX) { - printk(BIOS_INFO, "%s: Locking pad %d TX state\n", __func__, - pad); - msg.offset = msg.offset + 4; - status = pcr_execute_sideband_msg(&msg, &data, &response); - if (status || response) { - printk(BIOS_ERR, "%s: error status=%x response=%x\n", __func__, status, - response); - p2sb_hide(); - return status == -1 ? -1 : response; + comm = gpio_get_community(pad); + rel_pad = relative_pad_in_comm(comm, pad); + offset = comm->pad_cfg_lock_offset; + if (!offset) { + printk(BIOS_ERR, "%s: Error: offset not defined for pad %d!\n", + __func__, pad); + continue; + } + offset += gpio_group_index_scaled(comm, rel_pad, 2 * sizeof(uint32_t)); + + data = gpio_bitmask_within_group(comm, rel_pad); + msg.pid = comm->port; + msg.offset = offset; + + if (action & GPIO_LOCK_CONFIG) { + if (CONFIG(DEBUG_GPIO)) + printk(BIOS_INFO, "%s: Locking pad %d configuration\n", + __func__, pad); + status = pcr_execute_sideband_msg(&msg, &data, &response); + if ((err = sideband_msg_err(status, response)) != 0) { + err_response = err; + continue; + } + } + + if (action & GPIO_LOCK_TX) { + if (CONFIG(DEBUG_GPIO)) + printk(BIOS_INFO, "%s: Locking pad %d TX state\n", + __func__, pad); + msg.offset += 4; + status = pcr_execute_sideband_msg(&msg, &data, &response); + if ((err = sideband_msg_err(status, response)) != 0) { + err_response = err; + continue; + } } } p2sb_hide(); - return 0; + + return err_response; +} + +int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action action) +{ + const struct gpio_lock_config pads = { + .gpio = pad, + .action = action + }; + + return gpio_lock_pads(&pads, 1); } void gpio_set(gpio_t gpio_num, int value) diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index c47f908..91f9abe 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -205,6 +205,11 @@ GPIO_LOCK_FULL = GPIO_LOCK_CONFIG | GPIO_LOCK_TX, }; +struct gpio_lock_config { + gpio_t gpio; + enum gpio_lock_action action; +}; + /* * Lock a GPIO's configuration. * @@ -232,6 +237,33 @@ int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action action); /* + * gpio_lock_pads() can be used to lock an array of gpio pads, avoiding + * the p2sb_unhide() and p2sb_hide() calls between each gpio lock that would + * occur if gpio_lock_pad() were used to lock each pad in the list. + * + * @param pad_list: array of gpio_lock_config structures, one for each gpio to lock + * @param count: number of gpio_lock_config structs in the pad_list array + * @return 0 if successful, + * 1 - unsuccessful + * 2 - powered down + * 3 - multi-cast mixed + * -1 - sideband message failed or other error + */ +int gpio_lock_pads(const struct gpio_lock_config *pad_list, const size_t count); + +/* + * Returns an array of gpio_lock_config entries that the SoC + * deems security risks that should be locked down. + */ +const struct gpio_lock_config *soc_gpio_lock_config(size_t *num); + +/* + * Returns an array of gpio_lock_config entries that the mainboard + * deems security risks that should be locked down. + */ +const struct gpio_lock_config *mb_gpio_lock_config(size_t *num); + +/* * Returns the pmc_gpe to gpio_gpe mapping table * */ diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index 77ba00c..2d960d6 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -8,6 +8,13 @@ help Intel Processor trap flag if it is supported +config SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS + bool + help + Enable locking of security-sensitive SoC and mainboard GPIOs. + An SoC may provide a list of gpios to lock, and the mainboard + may also provide a list of gpios to lock. + config SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE bool default n diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index e1eadb6..32de2f6 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -311,6 +311,40 @@ } } +__weak const struct gpio_lock_config *soc_gpio_lock_config(size_t *num) +{ + *num = 0; + return NULL; +} + +__weak const struct gpio_lock_config *mb_gpio_lock_config(size_t *num) +{ + *num = 0; + return NULL; +} + +static void soc_lock_gpios(void) +{ + const struct gpio_lock_config *soc_gpios; + const struct gpio_lock_config *mb_gpios; + size_t soc_gpio_num; + size_t mb_gpio_num; + + /* get list of gpios from SoC */ + soc_gpios = soc_gpio_lock_config(&soc_gpio_num); + + /* get list of gpios from mainboard */ + mb_gpios = mb_gpio_lock_config(&mb_gpio_num); + + /* Lock any soc requested gpios */ + if (soc_gpio_num) + gpio_lock_pads(soc_gpios, soc_gpio_num); + + /* Lock any mainboard requested gpios */ + if (mb_gpio_num) + gpio_lock_pads(mb_gpios, mb_gpio_num); +} + static void finalize(void) { static int finalize_done; @@ -337,6 +371,10 @@ */ mainboard_smi_finalize(); + /* Lock down all GPIOs that may have been requested by the SoC and/or the mainboard. */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS)) + soc_lock_gpios(); + /* Specific SOC SMI handler during ramstage finalize phase */ smihandler_soc_at_finalize(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Gerrit-Change-Number: 58351 Gerrit-PatchSet: 14 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boris Mittelberg <bmbm(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3
by Cliff Huang (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59855 ) Change subject: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3 ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/pcie/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/59855/comment/24e5aaf1_e1d6eb35 PS2, Line 39: #define PCH_PCIE_CFG_LCAP_PN 0x4f /* Root Port Number */ Can we take this chance to clarify LCAP address? It should be 0x4C according to PCH EDS vol2 spec. -- To view, visit https://review.coreboot.org/c/coreboot/+/59855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d Gerrit-Change-Number: 59855 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 00:04:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: brya4es: sync CB:58374 from brya0
by YH Lin (Code Review) 06 Dec '21

06 Dec '21

YH Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59935 ) Change subject: brya4es: sync CB:58374 from brya0 ...................................................................... brya4es: sync CB:58374 from brya0 Sync'ing changes from brya0 (CB:58374). BUG=None TEST=build Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: I97489343b8f7a5b9457cd6f4a61cc37cd10ab450 --- M src/mainboard/google/brya/variants/brya4es/overridetree.cb 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/59935/1 diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb index 6812f20..3822a2c 100644 --- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb @@ -522,18 +522,19 @@ end end chip drivers/intel/mipi_camera - register "acpi_hid" = ""INT3499"" + register "acpi_hid" = ""ACPI_DT_NAMESPACE_HID"" register "acpi_uid" = "1" register "acpi_name" = ""NVM1"" register "chip_name" = ""GT24C16S"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC"" + register "nvm_compat" = ""atmel,24c1024"" - register "nvm_size" = "0x2800" + register "nvm_size" = "0x800" register "nvm_pagesize" = "0x01" register "nvm_readonly" = "0x01" - register "nvm_width" = "0x0E" + register "nvm_width" = "0x08" device i2c 50 on probe UFC UFC_MIPI_IMX208 -- To view, visit https://review.coreboot.org/c/coreboot/+/59935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97489343b8f7a5b9457cd6f4a61cc37cd10ab450 Gerrit-Change-Number: 59935 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTME] sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in S...
by Felix Held (Code Review) 06 Dec '21

06 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59934 ) Change subject: [TESTME] sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE ...................................................................... [TESTME] sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities. Haven't checked the reference code, but the register descriptions suggested that the register in Mullins behaves similar to the one in Stoneyridge. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifbd960a9509542b28f03326a3066995540260bef --- M src/southbridge/amd/pi/hudson/early_setup.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59934/1 diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 20597d4..2617985 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -215,7 +215,8 @@ (fast << SPI_FAST_SPEED_NEW_SH) | (alt << SPI_ALT_SPEED_NEW_SH) | (tpm << SPI_TPM_SPEED_NEW_SH)); - write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); + write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100 | + read16((void *)(base + SPI100_ENABLE))); } void hudson_disable_4dw_burst(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/59934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbd960a9509542b28f03326a3066995540260bef Gerrit-Change-Number: 59934 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit December 2021