coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/common: add generic gpio lock mechanism
by Tim Wawrzynczak (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Bora Guvendik, Caveh Jalali, Selma Bensaid, Maulik V Vaghela, Subrata Banik, Nick Vaccaro, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58351 ) Change subject: soc/intel/common: add generic gpio lock mechanism ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Gerrit-Change-Number: 58351 Gerrit-PatchSet: 13 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boris Mittelberg <bmbm(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 21:46:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/up/whl: Add UP Xtreme mainboard
by Felix Singer (Code Review) 06 Dec '21

06 Dec '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59927 ) Change subject: mb/up/whl: Add UP Xtreme mainboard ...................................................................... mb/up/whl: Add UP Xtreme mainboard Change-Id: Iac342f1c70f900247f2d5818edf5c9b64af44670 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A src/mainboard/up/whl/Kconfig A src/mainboard/up/whl/Kconfig.name A src/mainboard/up/whl/Makefile.inc A src/mainboard/up/whl/board_info.txt A src/mainboard/up/whl/bootblock.c A src/mainboard/up/whl/dsdt.asl A src/mainboard/up/whl/include/variant/gpio.h A src/mainboard/up/whl/include/variant/romstage.h A src/mainboard/up/whl/romstage.c A src/mainboard/up/whl/variants/xtreme/devicetree.cb A src/mainboard/up/whl/variants/xtreme/gpio.c A src/mainboard/up/whl/variants/xtreme/gpio_early.c A src/mainboard/up/whl/variants/xtreme/hda_verb.c A src/mainboard/up/whl/variants/xtreme/romstage.c 14 files changed, 299 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/59927/1 diff --git a/src/mainboard/up/whl/Kconfig b/src/mainboard/up/whl/Kconfig new file mode 100644 index 0000000..a6ad3c5 --- /dev/null +++ b/src/mainboard/up/whl/Kconfig @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config BOARD_UP_WHL_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_WHISKEYLAKE + +config BOARD_UP_WHL_XTREME + select BOARD_UP_WHL_COMMON + +if BOARD_UP_WHL_COMMON + +config MAINBOARD_DIR + default "up/whl" + +config MAINBOARD_PART_NUMBER + default "Xtreme" if BOARD_UP_WHL_XTREME + +config VARIANT_DIR + default "xtreme" if BOARD_UP_WHL_XTREME + +config DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config UART_FOR_CONSOLE + default 0 + +config POST_IO + default n + +config CONSOLE_POST + default y + +endif diff --git a/src/mainboard/up/whl/Kconfig.name b/src/mainboard/up/whl/Kconfig.name new file mode 100644 index 0000000..af434e7 --- /dev/null +++ b/src/mainboard/up/whl/Kconfig.name @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +comment "Whiskey Lake" + +config BOARD_UP_WHL_XTREME + bool "-> Xtreme" diff --git a/src/mainboard/up/whl/Makefile.inc b/src/mainboard/up/whl/Makefile.inc new file mode 100644 index 0000000..d2c5b0b --- /dev/null +++ b/src/mainboard/up/whl/Makefile.inc @@ -0,0 +1,12 @@ +CPPFLAGS_common += -I $(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +romstage-y += romstage.c +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/up/whl/board_info.txt b/src/mainboard/up/whl/board_info.txt new file mode 100644 index 0000000..ce30052 --- /dev/null +++ b/src/mainboard/up/whl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: UP +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/up/whl/bootblock.c b/src/mainboard/up/whl/bootblock.c new file mode 100644 index 0000000..b351fbd --- /dev/null +++ b/src/mainboard/up/whl/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <variant/gpio.h> + +void bootblock_mainboard_early_init(void) +{ + variant_configure_early_gpios(); +} diff --git a/src/mainboard/up/whl/dsdt.asl b/src/mainboard/up/whl/dsdt.asl new file mode 100644 index 0000000..e7963b2 --- /dev/null +++ b/src/mainboard/up/whl/dsdt.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/pc/ps2_controller.asl> + } +} diff --git a/src/mainboard/up/whl/include/variant/gpio.h b/src/mainboard/up/whl/include/variant/gpio.h new file mode 100644 index 0000000..95d5762 --- /dev/null +++ b/src/mainboard/up/whl/include/variant/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); + +#endif diff --git a/src/mainboard/up/whl/include/variant/romstage.h b/src/mainboard/up/whl/include/variant/romstage.h new file mode 100644 index 0000000..cfcc6ab --- /dev/null +++ b/src/mainboard/up/whl/include/variant/romstage.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_ROMSTAGE_H +#define VARIANT_ROMSTAGE_H + +void variant_configure_fspm(FSPM_UPD *memupd); + +#endif diff --git a/src/mainboard/up/whl/romstage.c b/src/mainboard/up/whl/romstage.c new file mode 100644 index 0000000..5ba6c56 --- /dev/null +++ b/src/mainboard/up/whl/romstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/romstage.h> +#include <variant/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + variant_configure_fspm(memupd); +} diff --git a/src/mainboard/up/whl/variants/xtreme/devicetree.cb b/src/mainboard/up/whl/variants/xtreme/devicetree.cb new file mode 100644 index 0000000..72be892 --- /dev/null +++ b/src/mainboard/up/whl/variants/xtreme/devicetree.cb @@ -0,0 +1,66 @@ +chip soc/intel/cannonlake + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + subsystemid 0x1558 0x1401 inherit + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal device + register "Device4Enable" = "1" + end + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 off end # CNVi wifi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 off end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 hidden end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/up/whl/variants/xtreme/gpio.c b/src/mainboard/up/whl/variants/xtreme/gpio.c new file mode 100644 index 0000000..fd6b0d9 --- /dev/null +++ b/src/mainboard/up/whl/variants/xtreme/gpio.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpe.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +/* Name format: <pad name> / <net/pin name in schematics> */ +static const struct pad_config gpio_table[] = { }; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/up/whl/variants/xtreme/gpio_early.c b/src/mainboard/up/whl/variants/xtreme/gpio_early.c new file mode 100644 index 0000000..0b4e22f --- /dev/null +++ b/src/mainboard/up/whl/variants/xtreme/gpio_early.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <variant/gpio.h> + +/* Name format: <pad name> / <net/pin name in schematics> */ +static const struct pad_config early_gpio_table[] = { }; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/up/whl/variants/xtreme/hda_verb.c b/src/mainboard/up/whl/variants/xtreme/hda_verb.c new file mode 100644 index 0000000..436e634 --- /dev/null +++ b/src/mainboard/up/whl/variants/xtreme/hda_verb.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { }; + +const u32 pc_beep_verbs[] = { }; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/up/whl/variants/xtreme/romstage.c b/src/mainboard/up/whl/variants/xtreme/romstage.c new file mode 100644 index 0000000..d1eff0f --- /dev/null +++ b/src/mainboard/up/whl/variants/xtreme/romstage.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <gpio.h> +#include <soc/cnl_memcfg_init.h> +#include <variant/romstage.h> + +static struct cnl_mb_cfg memcfg = { + .rcomp_resistor = { 121, 75, 100 }, + .rcomp_targets = { 60, 26, 20, 20, 26 }, + .dq_pins_interleaved = 0, +}; + +static uint8_t get_memory_variant(void) +{ + /* TODO: Fill in GPIO pads */ + const uint8_t memory_skuid_pads[] = { 0, 0 }; + uint8_t memory_variant = 0; + + for (uint8_t i = 0; i < ARRAY_SIZE(memory_skuid_pads); i++) { + uint8_t rx_state = gpio_get(memory_skuid_pads[i]); + memory_variant |= rx_state << i; + } + return memory_variant; +} + +void variant_configure_fspm(FSPM_UPD *memupd) +{ + uint8_t memory_variant = get_memory_variant(); + + switch (memory_variant) { + case 0: /* 16G (Channel A & B) */ + memcfg->spd[0] = { + .read_type = READ_SPD_CBFS, + .spd_spec = {.spd_index = 0}, /* TODO: Fix index */ + }; + memcfg.spd[2] = { + .read_type = READ_SPD_CBFS, + .spd_spec = {.spd_index = 0}, /* TODO: Fix index */ + }; + break; + case 1: /* 8G (Channel A) */ + &memcfg->spd[0] = { + .read_type = READ_SPD_CBFS, + .spd_spec = {.spd_index = 0}, /* TODO: Fix index */ + }; + break; + case 2: /* 8G (Channel A & B) */ + &memcfg->spd[0] = { + .read_type = READ_SPD_CBFS, + .spd_spec = {.spd_index = 0}, /* TODO: Fix index */ + }; + &memcfg->spd[2] = { + .read_type = READ_SPD_CBFS, + .spd_spec = {.spd_index = 0}, /* TODO: Fix index */ + }; + break; + case 3: /* 4G (Channel A) */ + &memcfg->spd[0] = { + .read_type = READ_SPD_CBFS, + .spd_spec = {.spd_index = 0}, /* TODO: Fix index */ + }; + break; + default: + printk(BIOS_ERR, "%s: No supported memory found!\n", __func__); + break; + } + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac342f1c70f900247f2d5818edf5c9b64af44670 Gerrit-Change-Number: 59927 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Hook up DPTF device to devicetree
by Tim Wawrzynczak (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Felix Singer, Jeremy Soller, Nick Vaccaro, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59886 ) Change subject: soc/intel/tigerlake: Hook up DPTF device to devicetree ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Gerrit-Change-Number: 59886 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 21:46:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/liveiso: Update to NixOS 21.11
by Felix Singer (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Michael Niewöhner. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59881 ) Change subject: util/liveiso: Update to NixOS 21.11 ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/59881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9a382b83b3b3e55126bb0bb508659d11497a05 Gerrit-Change-Number: 59881 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 06 Dec 2021 21:45:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Hook up SMBus device to devicetree
by Tim Wawrzynczak (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Felix Singer, Sean Rhodes, Jeremy Soller, Nick Vaccaro, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59883 ) Change subject: soc/intel/tigerlake: Hook up SMBus device to devicetree ...................................................................... Patch Set 7: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59883/comment/d1d1f20b_2c4b7dd9 PS7, Line 9: devicetree suggestion: `to the enabled status of the smbus device in the devicetree` Patchset: PS7: > I prefer you do that in a separate commit so that this one doesn't change the current state. Thanks, google/deltaur will be dropped from the tree soon so it is irrelevant. -- To view, visit https://review.coreboot.org/c/coreboot/+/59883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Gerrit-Change-Number: 59883 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 21:44:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Enable SMBus in Device Tree
by Sean Rhodes (Code Review) 06 Dec '21

06 Dec '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59926 ) Change subject: mb/starlabs/labtop: Enable SMBus in Device Tree ...................................................................... mb/starlabs/labtop: Enable SMBus in Device Tree Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I8bc3025331bb25b02712b5d2b654f7997f0aba4a --- M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/59926/1 diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index c8abce9..5c55dce 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -232,7 +232,7 @@ subsystemid 0x10ec 0x1200 register "PchHdaAudioLinkHdaEnable" = "1" end - device pci 1f.4 off end # SMBus + device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE device pci 1f.7 off end # TH -- To view, visit https://review.coreboot.org/c/coreboot/+/59926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bc3025331bb25b02712b5d2b654f7997f0aba4a Gerrit-Change-Number: 59926 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Drop unused SataEnable setting
by Tim Wawrzynczak (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Felix Singer, Nick Vaccaro, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59884 ) Change subject: soc/intel/tigerlake: Drop unused SataEnable setting ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82 Gerrit-Change-Number: 59884 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 21:43:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Hook up SMBus device to devicetree
by Felix Singer (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Sean Rhodes, Jeremy Soller, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59883 ) Change subject: soc/intel/tigerlake: Hook up SMBus device to devicetree ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > Nice. […] I prefer you do that in a separate commit so that this one doesn't change the current state. -- To view, visit https://review.coreboot.org/c/coreboot/+/59883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Gerrit-Change-Number: 59883 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 21:30:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_init
by Rob Barnes (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59922 ) Change subject: mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_init ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130 Gerrit-Change-Number: 59922 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Dec 2021 21:04:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Combine mem_parts_used.txt
by Raul Rangel (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Chris Wang, Rob Barnes, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59923 ) Change subject: mb/google/guybrush: Combine mem_parts_used.txt ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie17025e092f2b9397afea33fce285e80ef5dc995 Gerrit-Change-Number: 59923 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 06 Dec 2021 20:55:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021