coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/corsola: get SKU ID from EC (CBI)
by Rex-BC Chen (Code Review) 07 Dec '21

07 Dec '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59944 ) Change subject: mb/google/corsola: get SKU ID from EC (CBI) ...................................................................... mb/google/corsola: get SKU ID from EC (CBI) The SKU ID for Corsola is retrieved via CBI interface. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I2888190d498df28b5ae13cf92cc41d088e8f8ee7 --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/boardid.c 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/59944/1 diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 8877f2f..193cafd 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -23,6 +23,7 @@ select COMMONLIB_STORAGE_MMC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT diff --git a/src/mainboard/google/corsola/boardid.c b/src/mainboard/google/corsola/boardid.c index 285b065..96031ef 100644 --- a/src/mainboard/google/corsola/boardid.c +++ b/src/mainboard/google/corsola/boardid.c @@ -3,6 +3,7 @@ #include <assert.h> #include <boardid.h> #include <console/console.h> +#include <ec/google/chromeec/ec.h> #include <soc/auxadc.h> /* board_id is provided by ec/google/chromeec/ec_boardid.c */ @@ -13,6 +14,9 @@ /* RAM IDs */ RAM_ID_LOW_CHANNEL = 2, RAM_ID_HIGH_CHANNEL = 3, + /* SKU IDs */ + SKU_ID_LOW_CHANNEL = 4, + SKU_ID_HIGH_CHANNEL = 5, }; static const unsigned int ram_voltages[ADC_LEVELS] = { @@ -34,6 +38,8 @@ static const unsigned int *adc_voltages[] = { [RAM_ID_LOW_CHANNEL] = ram_voltages, [RAM_ID_HIGH_CHANNEL] = ram_voltages, + [SKU_ID_LOW_CHANNEL] = ram_voltages, + [SKU_ID_HIGH_CHANNEL] = ram_voltages, }; static uint32_t get_adc_index(unsigned int channel) @@ -54,6 +60,24 @@ return id; } +uint32_t sku_id(void) +{ + static uint32_t cached_sku_code = BOARD_ID_INIT; + + if (cached_sku_code == BOARD_ID_INIT) { + cached_sku_code = google_chromeec_get_board_sku(); + + if (cached_sku_code == CROS_SKU_UNKNOWN) { + printk(BIOS_WARNING, "Failed to get SKU code from EC\n"); + cached_sku_code = (get_adc_index(SKU_ID_HIGH_CHANNEL) << 4 | + get_adc_index(SKU_ID_LOW_CHANNEL)); + } + printk(BIOS_DEBUG, "SKU Code: %#02x\n", cached_sku_code); + } + + return cached_sku_code; +} + uint32_t ram_code(void) { static uint32_t cached_ram_code = BOARD_ID_INIT; -- To view, visit https://review.coreboot.org/c/coreboot/+/59944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2888190d498df28b5ae13cf92cc41d088e8f8ee7 Gerrit-Change-Number: 59944 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: Configure TPM
by Rex-BC Chen (Code Review) 07 Dec '21

07 Dec '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59943 ) Change subject: mb/google/corsola: Configure TPM ...................................................................... mb/google/corsola: Configure TPM Initialize SPI bus 2 for TPM control. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I8ede68d6eb594890195e8464151c1c0f88aeee43 --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/bootblock.c M src/mainboard/google/corsola/chromeos.c 3 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/59943/1 diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 2a935f3..8877f2f 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -24,6 +24,8 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT config MAINBOARD_DIR string @@ -43,6 +45,10 @@ bool default n +config DRIVER_TPM_SPI_BUS + hex + default 0x2 + config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0x1 diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c index d742074..ea36fed 100644 --- a/src/mainboard/google/corsola/bootblock.c +++ b/src/mainboard/google/corsola/bootblock.c @@ -9,6 +9,8 @@ void bootblock_mainboard_init(void) { mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); mtk_snfc_init(SPI_NOR_GPIO_SET0); setup_chromeos_gpios(); + gpio_eint_configure(GPIO_GSC_AP_INT, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c index 84023b7..847569e 100644 --- a/src/mainboard/google/corsola/chromeos.c +++ b/src/mainboard/google/corsola/chromeos.c @@ -3,6 +3,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <security/tpm/tis.h> #include "gpio.h" @@ -32,3 +33,8 @@ /* EC is trusted if not in RW. This is active low. */ return !!gpio_get(GPIO_EC_IN_RW); } + +int tis_plat_irq_status(void) +{ + return gpio_eint_poll(GPIO_GSC_AP_INT); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ede68d6eb594890195e8464151c1c0f88aeee43 Gerrit-Change-Number: 59943 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: implement get_ec_is_trusted
by Rex-BC Chen (Code Review) 07 Dec '21

07 Dec '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59942 ) Change subject: mb/google/corsola: implement get_ec_is_trusted ...................................................................... mb/google/corsola: implement get_ec_is_trusted Set VB2_CONTEXT_EC_TRUSTED in verstage_main. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: If2837f5db52f91f5418d222d4dcd1af2aebcc105 --- M src/mainboard/google/corsola/chromeos.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/59942/1 diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c index 63c3f4c..84023b7 100644 --- a/src/mainboard/google/corsola/chromeos.c +++ b/src/mainboard/google/corsola/chromeos.c @@ -26,3 +26,9 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. This is active low. */ + return !!gpio_get(GPIO_EC_IN_RW); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2837f5db52f91f5418d222d4dcd1af2aebcc105 Gerrit-Change-Number: 59942 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: Enable Chrome EC
by Rex-BC Chen (Code Review) 07 Dec '21

07 Dec '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59941 ) Change subject: mb/google/corsola: Enable Chrome EC ...................................................................... mb/google/corsola: Enable Chrome EC Initialize SPI bus 1 for Chrome EC control. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I7d032d595f7ca1dbed3de4dfe308ff4be64333cd --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/bootblock.c M src/mainboard/google/corsola/chromeos.c M src/mainboard/google/corsola/reset.c 4 files changed, 17 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/59941/1 diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index b57e23b..2a935f3 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -6,16 +6,24 @@ if BOARD_GOOGLE_CORSOLA_COMMON +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_MEDIATEK_MT8186 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select SPI_FLASH_INCLUDE_ALL_DRIVERS select COMMONLIB_STORAGE select COMMONLIB_STORAGE_MMC + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SPI config MAINBOARD_DIR string @@ -34,4 +42,8 @@ config SDCARD_INIT bool default n + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x1 endif diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c index bb76b98..d742074 100644 --- a/src/mainboard/google/corsola/bootblock.c +++ b/src/mainboard/google/corsola/bootblock.c @@ -8,6 +8,7 @@ void bootblock_mainboard_init(void) { + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_snfc_init(SPI_NOR_GPIO_SET0); setup_chromeos_gpios(); } diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c index 6a727c9..63c3f4c 100644 --- a/src/mainboard/google/corsola/chromeos.c +++ b/src/mainboard/google/corsola/chromeos.c @@ -26,9 +26,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_recovery_mode_switch(void) -{ - /* TODO: use Chrome EC switches when EC support is added */ - return 0; -} diff --git a/src/mainboard/google/corsola/reset.c b/src/mainboard/google/corsola/reset.c index 3a97ee5..91ee7c0 100644 --- a/src/mainboard/google/corsola/reset.c +++ b/src/mainboard/google/corsola/reset.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <gpio.h> #include <reset.h> +#include "gpio.h" + void do_board_reset(void) { + gpio_output(GPIO_RESET, 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d032d595f7ca1dbed3de4dfe308ff4be64333cd Gerrit-Change-Number: 59941 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: revise SPI NOR GPIO selection
by Rex-BC Chen (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59940 ) Change subject: soc/mediatek/mt8186: revise SPI NOR GPIO selection ...................................................................... soc/mediatek/mt8186: revise SPI NOR GPIO selection The setting of SPI NOR GPIOs should be: CS: pull up. CLK/IO0/IO1: pull down. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ideacb797a1dc9999ab6ba00cf33adbbbc24213dc --- M src/soc/mediatek/mt8186/spi.c 1 file changed, 13 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/59940/1 diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c index 87f669d..d4d3684 100644 --- a/src/soc/mediatek/mt8186/spi.c +++ b/src/soc/mediatek/mt8186/spi.c @@ -43,10 +43,12 @@ struct pad_func { gpio_t gpio; u8 func; + enum pull_select select; }; -#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} -#define PAD_FUNC_GPIO(name) {GPIO(name), 0} +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func, GPIO_PULL_DOWN} +#define PAD_FUNC_SEL(name, func, sel) {GPIO(name), PAD_##name##_FUNC_##func, sel} +#define PAD_FUNC_GPIO(name) {GPIO(name), 0, GPIO_PULL_DOWN} static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { { @@ -121,17 +123,17 @@ static const struct pad_func nor_pinmux[SPI_NOR_GPIO_SET_NUM][4] = { /* GPIO 36 ~ 39 */ [SPI_NOR_GPIO_SET0] = { - PAD_FUNC(SPI0_CLK, SPINOR_CK), - PAD_FUNC(SPI0_CSB, SPINOR_CS), - PAD_FUNC(SPI0_MO, SPINOR_IO0), - PAD_FUNC(SPI0_MI, SPINOR_IO1), + PAD_FUNC_SEL(SPI0_CLK, SPINOR_CK, GPIO_PULL_DOWN), + PAD_FUNC_SEL(SPI0_CSB, SPINOR_CS, GPIO_PULL_UP), + PAD_FUNC_SEL(SPI0_MO, SPINOR_IO0, GPIO_PULL_DOWN), + PAD_FUNC_SEL(SPI0_MI, SPINOR_IO1, GPIO_PULL_DOWN), }, /* GPIO 61 ~ 64 */ [SPI_NOR_GPIO_SET1] = { - PAD_FUNC(TDM_RX_BCK, SPINOR_CK), - PAD_FUNC(TDM_RX_MCLK, SPINOR_CS), - PAD_FUNC(TDM_RX_DATA0, SPINOR_IO0), - PAD_FUNC(TDM_RX_DATA1, SPINOR_IO1), + PAD_FUNC_SEL(TDM_RX_BCK, SPINOR_CK, GPIO_PULL_DOWN), + PAD_FUNC_SEL(TDM_RX_MCLK, SPINOR_CS, GPIO_PULL_UP), + PAD_FUNC_SEL(TDM_RX_DATA0, SPINOR_IO0, GPIO_PULL_DOWN), + PAD_FUNC_SEL(TDM_RX_DATA1, SPINOR_IO1, GPIO_PULL_DOWN), }, }; @@ -143,7 +145,7 @@ ptr = nor_pinmux[gpio_set]; for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux[gpio_set]); i++) { - gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, ptr[i].select); gpio_set_mode(ptr[i].gpio, ptr[i].func); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/59940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ideacb797a1dc9999ab6ba00cf33adbbbc24213dc Gerrit-Change-Number: 59940 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Correct SPI_HZ for PLL
by Rex-BC Chen (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59939 ) Change subject: soc/mediatek/mt8186: Correct SPI_HZ for PLL ...................................................................... soc/mediatek/mt8186: Correct SPI_HZ for PLL The SPI speed is 218.4MHz, so correct the value of SPI_HZ. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I6e8ba10a851e1507405cdd41939a176462734487 --- M src/soc/mediatek/mt8186/include/soc/pll.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/59939/1 diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h index ce98077..c2dace3 100644 --- a/src/soc/mediatek/mt8186/include/soc/pll.h +++ b/src/soc/mediatek/mt8186/include/soc/pll.h @@ -492,12 +492,12 @@ /* top_div rate */ enum { CLK26M_HZ = 26 * MHz, - UNIVPLL_D6_D2_HZ = UNIV2PLL_HZ / 2 / 6 / 2, + MAINPLL_D5_HZ = MAINPLL_HZ / 5, }; /* top_mux rate */ enum { - SPI_HZ = UNIVPLL_D6_D2_HZ, + SPI_HZ = MAINPLL_D5_HZ, UART_HZ = CLK26M_HZ, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8ba10a851e1507405cdd41939a176462734487 Gerrit-Change-Number: 59939 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: Pass reset gpio parameter to BL31
by Rex-BC Chen (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Paul Menzel. Hello Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59824 to look at the new patch set (#2). Change subject: mb/google/corsola: Pass reset gpio parameter to BL31 ...................................................................... mb/google/corsola: Pass reset gpio parameter to BL31 To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. TEST=build pass BUG=b:202871018 Cq-Depend: chromium:3188686 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I48d8d004ea92e950d0040a11133c57c121b86af3 --- M src/mainboard/google/corsola/mainboard.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/59824/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48d8d004ea92e950d0040a11133c57c121b86af3 Gerrit-Change-Number: 59824 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: update DRAM ID table for all variants
by Chris Wang (Code Review) 07 Dec '21

07 Dec '21

Chris Wang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59920 ) Change subject: mb/google/guybrush: update DRAM ID table for all variants ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/59920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc21f1a032e97cf30d7eb072bbf6894c01e8bbc Gerrit-Change-Number: 59920 Gerrit-PatchSet: 3 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/intel/adlrvp_n: Add initial code for adl-n variant board
by Krishna P Bhat D (Code Review) 07 Dec '21

07 Dec '21

Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59915 ) Change subject: mb/intel/adlrvp_n: Add initial code for adl-n variant board ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/59915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad Gerrit-Change-Number: 59915 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 02:34:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cse: config to enable oem key manifest
by Krishna P Bhat D (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Ravindra, Arthur Heymans, Patrick Rudolph, Ravindra N. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59895 ) Change subject: soc/intel/cse: config to enable oem key manifest ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3620adb2898efc002104e0ba8b2afd219c31f230 Gerrit-Change-Number: 59895 Gerrit-PatchSet: 5 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 07 Dec 2021 02:16:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021