coreboot-gerrit December 2021

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Change in coreboot[master]: security/intel: Use defines for segment registers
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Patrick Rudolph. Patrick Georgi has uploaded a new patch set (#2) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/59763 ) Change subject: security/intel: Use defines for segment registers ...................................................................... security/intel: Use defines for segment registers Change-Id: I6f11039bafa3800d59d61defa8824ae962224c9b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/intel/txt/getsec_enteraccs.S 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/59763/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f11039bafa3800d59d61defa8824ae962224c9b Gerrit-Change-Number: 59763 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cbfs: Remove deprecated APIs
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59682 ) Change subject: cbfs: Remove deprecated APIs ...................................................................... cbfs: Remove deprecated APIs This patch removes all remaining pieces of the old CBFS API, now that the last straggling use cases of it have been ported to the new one (meaning cbfs_map()/cbfs_load()/etc... see CB:39304 and CB:38421). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59682 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/commonlib/Makefile.inc D src/commonlib/cbfs.c D src/commonlib/include/commonlib/cbfs.h M src/include/cbfs.h M src/lib/cbfs.c M src/security/tpm/tspi/crtm.h M src/security/vboot/Kconfig M tests/lib/cbfs-lookup-test.c M tests/lib/cbfs-verification-test.c 9 files changed, 5 insertions(+), 483 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Raul Rangel: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 9347f88..2477e07 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -27,13 +27,6 @@ endif ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c -bootblock-y += cbfs.c -verstage-y += cbfs.c -romstage-y += cbfs.c -ramstage-y += cbfs.c -smm-y += cbfs.c -postcar-y += cbfs.c - bootblock-y += bsd/cbfs_private.c verstage-y += bsd/cbfs_private.c romstage-y += bsd/cbfs_private.c diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c deleted file mode 100644 index e7f800c..0000000 --- a/src/commonlib/cbfs.c +++ /dev/null @@ -1,347 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <commonlib/cbfs.h> -#include <commonlib/endian.h> -#include <commonlib/helpers.h> -#include <string.h> -#include <vb2_sha.h> - -static size_t cbfs_next_offset(const struct region_device *cbfs, - const struct cbfsf *f) -{ - size_t offset; - - if (f == NULL) - return 0; - - /* The region_device objects store absolute offsets over the whole - * region. Therefore a relative offset needs to be calculated. */ - offset = rdev_relative_offset(cbfs, &f->data); - offset += region_device_sz(&f->data); - - return ALIGN_UP(offset, CBFS_ALIGNMENT); -} - -static int cbfs_end(const struct region_device *cbfs, size_t offset) -{ - if (offset >= region_device_sz(cbfs)) - return 1; - - return 0; -} - -int cbfs_for_each_file(const struct region_device *cbfs, - const struct cbfsf *prev, struct cbfsf *fh) -{ - size_t offset; - - offset = cbfs_next_offset(cbfs, prev); - - /* Try to scan the entire cbfs region looking for file name. */ - while (1) { - struct cbfs_file file; - const size_t fsz = sizeof(file); - - DEBUG("Checking offset %zx\n", offset); - - /* End of region. */ - if (cbfs_end(cbfs, offset)) - return 1; - - /* Can't read file. Nothing else to do but bail out. */ - if (rdev_readat(cbfs, &file, offset, fsz) != fsz) - break; - - if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) { - offset++; - offset = ALIGN_UP(offset, CBFS_ALIGNMENT); - continue; - } - - file.len = read_be32(&file.len); - file.offset = read_be32(&file.offset); - - DEBUG("File @ offset %zx size %x\n", offset, file.len); - - /* Keep track of both the metadata and the data for the file. */ - if (rdev_chain(&fh->metadata, cbfs, offset, file.offset)) - break; - - if (rdev_chain(&fh->data, cbfs, offset + file.offset, file.len)) - break; - - /* Success. */ - return 0; - } - - return -1; -} - -size_t cbfs_for_each_attr(void *metadata, size_t metadata_size, - size_t last_offset) -{ - struct cbfs_file_attribute *attr; - - if (!last_offset) { - struct cbfs_file *file = metadata; - size_t start_offset = read_be32(&file->attributes_offset); - if (start_offset <= sizeof(struct cbfs_file) || - start_offset + sizeof(*attr) > metadata_size) - return 0; - return start_offset; - } - - attr = metadata + last_offset; - size_t next_offset = last_offset + read_be32(&attr->len); - - if (next_offset + sizeof(*attr) > metadata_size) - return 0; - return next_offset; -} - -int cbfsf_decompression_info(struct cbfsf *fh, uint32_t *algo, size_t *size) -{ - size_t metadata_size = region_device_sz(&fh->metadata); - void *metadata = rdev_mmap_full(&fh->metadata); - size_t offs = 0; - - if (!metadata) - return -1; - - while ((offs = cbfs_for_each_attr(metadata, metadata_size, offs))) { - struct cbfs_file_attr_compression *attr = metadata + offs; - if (read_be32(&attr->tag) != CBFS_FILE_ATTR_TAG_COMPRESSION) - continue; - - *algo = read_be32(&attr->compression); - *size = read_be32(&attr->decompressed_size); - rdev_munmap(&fh->metadata, metadata); - return 0; - } - - *algo = CBFS_COMPRESS_NONE; - *size = region_device_sz(&fh->data); - rdev_munmap(&fh->metadata, metadata); - return 0; -} - -int cbfsf_file_type(struct cbfsf *fh, uint32_t *ftype) -{ - const size_t sz = sizeof(*ftype); - - if (rdev_readat(&fh->metadata, ftype, - offsetof(struct cbfs_file, type), sz) != sz) - return -1; - - *ftype = read_be32(ftype); - - return 0; -} - -int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, - const char *name, uint32_t *type) -{ - struct cbfsf *prev; - - LOG("Locating '%s'\n", name); - - prev = NULL; - - while (1) { - int ret; - char *fname; - int name_match; - const size_t fsz = sizeof(struct cbfs_file); - - ret = cbfs_for_each_file(cbfs, prev, fh); - prev = fh; - - /* Either failed to read or hit the end of the region. */ - if (ret < 0 || ret > 0) - break; - - fname = rdev_mmap(&fh->metadata, fsz, - region_device_sz(&fh->metadata) - fsz); - - if (fname == NULL) - break; - - name_match = !strcmp(fname, name); - rdev_munmap(&fh->metadata, fname); - - if (!name_match) { - DEBUG(" Unmatched '%s' at %zx\n", fname, - rdev_relative_offset(cbfs, &fh->metadata)); - continue; - } - - if (type != NULL) { - uint32_t ftype; - - if (cbfsf_file_type(fh, &ftype)) - break; - - if (*type != 0 && *type != ftype) { - DEBUG(" Unmatched type %x at %zx\n", ftype, - rdev_relative_offset(cbfs, - &fh->metadata)); - continue; - } - // *type being 0 means we want to know ftype. - // We could just do a blind assignment but - // if type is pointing to read-only memory - // that might be bad. - if (*type == 0) - *type = ftype; - } - - LOG("Found @ offset %zx size %zx\n", - rdev_relative_offset(cbfs, &fh->metadata), - region_device_sz(&fh->data)); - - /* Success. */ - return 0; - } - - LOG("'%s' not found.\n", name); - return -1; -} - -static int cbfs_extend_hash_buffer(struct vb2_digest_context *ctx, - void *buf, size_t sz) -{ - return vb2_digest_extend(ctx, buf, sz); -} - -static int cbfs_extend_hash(struct vb2_digest_context *ctx, - const struct region_device *rdev) -{ - uint8_t buffer[1024]; - size_t sz_left; - size_t offset; - - sz_left = region_device_sz(rdev); - offset = 0; - - while (sz_left) { - int rv; - size_t block_sz = MIN(sz_left, sizeof(buffer)); - - if (rdev_readat(rdev, buffer, offset, block_sz) != block_sz) - return VB2_ERROR_UNKNOWN; - - rv = cbfs_extend_hash_buffer(ctx, buffer, block_sz); - - if (rv) - return rv; - - sz_left -= block_sz; - offset += block_sz; - } - - return VB2_SUCCESS; -} - -/* Include offsets of child regions within the parent into the hash. */ -static int cbfs_extend_hash_with_offset(struct vb2_digest_context *ctx, - const struct region_device *p, - const struct region_device *c) -{ - int32_t soffset; - int rv; - - soffset = rdev_relative_offset(p, c); - - if (soffset < 0) - return VB2_ERROR_UNKNOWN; - - /* All offsets in big endian format. */ - write_be32(&soffset, soffset); - - rv = cbfs_extend_hash_buffer(ctx, &soffset, sizeof(soffset)); - - if (rv) - return rv; - - return cbfs_extend_hash(ctx, c); -} - -/* Hash in the potential CBFS header sitting at the beginning of the CBFS - * region as well as relative offset at the end. */ -static int cbfs_extend_hash_master_header(struct vb2_digest_context *ctx, - const struct region_device *cbfs) -{ - struct region_device rdev; - int rv; - - if (rdev_chain(&rdev, cbfs, 0, sizeof(struct cbfs_header))) - return VB2_ERROR_UNKNOWN; - - rv = cbfs_extend_hash_with_offset(ctx, cbfs, &rdev); - - if (rv) - return rv; - - /* Include potential relative offset at end of region. */ - if (rdev_chain(&rdev, cbfs, region_device_sz(cbfs) - sizeof(int32_t), - sizeof(int32_t))) - return VB2_ERROR_UNKNOWN; - - return cbfs_extend_hash_with_offset(ctx, cbfs, &rdev); -} - -int cbfs_vb2_hash_contents(const struct region_device *cbfs, - enum vb2_hash_algorithm hash_alg, void *digest, - size_t digest_sz) -{ - struct vb2_digest_context ctx; - int rv; - struct cbfsf f; - struct cbfsf *prev; - struct cbfsf *fh; - - rv = vb2_digest_init(&ctx, hash_alg); - - if (rv) - return rv; - - rv = cbfs_extend_hash_master_header(&ctx, cbfs); - if (rv) - return rv; - - prev = NULL; - fh = &f; - - while (1) { - uint32_t ftype; - - rv = cbfs_for_each_file(cbfs, prev, fh); - prev = fh; - - if (rv < 0) - return VB2_ERROR_UNKNOWN; - - /* End of CBFS. */ - if (rv > 0) - break; - - rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->metadata); - - if (rv) - return rv; - - /* Include data contents in hash if file is non-empty. */ - if (cbfsf_file_type(fh, &ftype)) - return VB2_ERROR_UNKNOWN; - - if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_NULL) - continue; - - rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->data); - - if (rv) - return rv; - } - - return vb2_digest_finalize(&ctx, digest, digest_sz); -} diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h deleted file mode 100644 index 6565c1d..0000000 --- a/src/commonlib/include/commonlib/cbfs.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _COMMONLIB_CBFS_H_ -#define _COMMONLIB_CBFS_H_ - -#include <commonlib/bsd/cbfs_private.h> -#include <commonlib/region.h> -#include <vb2_api.h> - -/* Object representing cbfs files. */ -struct cbfsf { - struct region_device metadata; - struct region_device data; - union cbfs_mdata mdata; -}; - -/* Locate file by name and optional type. Returns 0 on success else < 0 on - * error.*/ -int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, - const char *name, uint32_t *type); - -static inline void cbfs_file_data(struct region_device *data, - const struct cbfsf *file) -{ - rdev_chain_full(data, &file->data); -} - -static inline void cbfs_file_metadata(struct region_device *metadata, - const struct cbfsf *file) -{ - rdev_chain_full(metadata, &file->metadata); -} - -/* - * Provide a handle to each cbfs file within a cbfs. The prev pointer represents - * the previous file (NULL on first invocation). The next object gets filled - * out with the next file. This returns < 0 on error, 0 on finding the next - * file, and > 0 at end of cbfs. - */ -int cbfs_for_each_file(const struct region_device *cbfs, - const struct cbfsf *prev, struct cbfsf *fh); - -/* - * Return the offset for each CBFS attribute in a CBFS file metadata region. - * The metadata must already be fully mapped by the caller. Will return the - * offset (relative to the start of the metadata) or 0 when there are no - * further attributes. Should be called with 0 to begin, then always with - * the previously returned value until it returns 0. - */ -size_t cbfs_for_each_attr(void *metadata, size_t metadata_size, - size_t last_offset); - -/* - * Find out the decompression algorithm and decompressed size of a non-stage - * CBFS file (by parsing its metadata attributes), and return them with - * out-parameters. Returns 0 on success and < 0 on error. - */ -int cbfsf_decompression_info(struct cbfsf *fh, uint32_t *algo, size_t *size); - -/* - * Return the CBFS file type as out-parameter. - * Returns 0 on success and < 0 on error. - */ -int cbfsf_file_type(struct cbfsf *fh, uint32_t *ftype); - -/* - * Perform the vb2 hash over the CBFS region skipping empty file contents. - * Caller is responsible for providing the hash algorithm as well as storage - * for the final digest. Return 0 on success or non-zero on error. - */ -int cbfs_vb2_hash_contents(const struct region_device *cbfs, - enum vb2_hash_algorithm hash_alg, void *digest, - size_t digest_sz); - -#endif diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 6c79625..5731d6e 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -5,9 +5,9 @@ #include <cbmem.h> #include <commonlib/bsd/cbfs_mdata.h> -#include <commonlib/cbfs.h> #include <commonlib/mem_pool.h> #include <commonlib/region.h> +#include <endian.h> #include <program_loading.h> #include <types.h> #include <vb2_sha.h> @@ -190,16 +190,6 @@ /********************************************************************************************** - * LEGACY APIs, TO BE DEPRECATED/REPLACED * - **********************************************************************************************/ - -/* Locate file by name and optional type. Return 0 on success. < 0 on error. */ -int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type); -/* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ -int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, - const char *name, uint32_t *type); - -/********************************************************************************************** * INTERNAL HELPERS FOR INLINES, DO NOT USE. * **********************************************************************************************/ cb_err_t _cbfs_boot_lookup(const char *name, bool force_ro, diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 0b58913..991c9fe 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -6,7 +6,6 @@ #include <cbmem.h> #include <commonlib/bsd/cbfs_private.h> #include <commonlib/bsd/compression.h> -#include <commonlib/endian.h> #include <console/console.h> #include <fmap.h> #include <lib.h> @@ -84,25 +83,6 @@ return CB_SUCCESS; } -int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) -{ - if (_cbfs_boot_lookup(name, false, &fh->mdata, &fh->data)) - return -1; - - size_t msize = be32toh(fh->mdata.h.offset); - if (rdev_chain_mem(&fh->metadata, &fh->mdata, msize)) - return -1; - - if (type) { - if (!*type) - *type = be32toh(fh->mdata.h.type); - else if (*type != be32toh(fh->mdata.h.type)) - return -1; - } - - return 0; -} - void cbfs_unmap(void *mapping) { /* @@ -115,26 +95,6 @@ mem_pool_free(&cbfs_cache, mapping); } -int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, - const char *name, uint32_t *type) -{ - struct region_device rdev; - int ret = 0; - if (fmap_locate_area_as_rdev(region_name, &rdev)) { - LOG("%s region not found while looking for %s\n", region_name, name); - return -1; - } - - uint32_t dummy_type = 0; - if (!type) - type = &dummy_type; - - ret = cbfs_locate(fh, &rdev, name, type); - /* No more measuring here, this function will be removed next patch. */ - - return ret; -} - static inline bool fsps_env(void) { /* FSP-S is assumed to be loaded in ramstage. */ diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index 8ebb661..c4d051d 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -3,7 +3,6 @@ #ifndef __SECURITY_TSPI_CRTM_H__ #define __SECURITY_TSPI_CRTM_H__ -#include <commonlib/cbfs.h> #include <program_loading.h> #include <security/tpm/tspi.h> #include <types.h> diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 26f2484..3e29c7e 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -251,8 +251,8 @@ default n depends on VBOOT_SLOTS_RW_A help - When this option is enabled cbfs_boot_locate will look for a file in the RO - (COREBOOT) region if it isn't available in the active RW region. + When this option is enabled, the CBFS code will look for a file in the + RO (COREBOOT) region if it isn't available in the active RW region. config VBOOT_EARLY_EC_SYNC bool diff --git a/tests/lib/cbfs-lookup-test.c b/tests/lib/cbfs-lookup-test.c index 27abca3..78481d7 100644 --- a/tests/lib/cbfs-lookup-test.c +++ b/tests/lib/cbfs-lookup-test.c @@ -3,6 +3,7 @@ #include <assert.h> #include <cbfs.h> #include <commonlib/bsd/cbfs_mdata.h> +#include <commonlib/bsd/cbfs_private.h> #include <commonlib/region.h> #include <string.h> #include <tests/lib/cbfs_util.h> diff --git a/tests/lib/cbfs-verification-test.c b/tests/lib/cbfs-verification-test.c index 3f35739..1f46c7d 100644 --- a/tests/lib/cbfs-verification-test.c +++ b/tests/lib/cbfs-verification-test.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbfs.h> +#include <commonlib/bsd/cbfs_private.h> #include <commonlib/region.h> #include <string.h> #include <tests/lib/cbfs_util.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/59682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Gerrit-Change-Number: 59682 Gerrit-PatchSet: 5 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: tests: Fix objcopy --add-symbol arguments creation
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59858 ) Change subject: tests: Fix objcopy --add-symbol arguments creation ...................................................................... tests: Fix objcopy --add-symbol arguments creation Remove unnecessary escape bachslashes from: addr="$(echo \"$$$$sym_line\" ... The 'echo' will print output line with double quote characters, which then will be included in the values passed to --add-symbol. This can cause errors. Change-Id: I6023515191d6c236bf57870159a35d518f25e9d8 Reported-by: Yu-Ping Wu <yupingso(a)chromium.org> Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59858 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M payloads/libpayload/tests/Makefile.inc M tests/Makefile.inc 2 files changed, 6 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/payloads/libpayload/tests/Makefile.inc b/payloads/libpayload/tests/Makefile.inc index c4463d7..bf484bb 100644 --- a/payloads/libpayload/tests/Makefile.inc +++ b/payloads/libpayload/tests/Makefile.inc @@ -141,8 +141,8 @@ sym_line="$$$$($(HOSTOBJDUMP) -t $$@.orig \ | grep -E "[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s+$$$$sym$$$$")"; \ if [ ! -z "$$$$sym_line" ] ; then \ - addr="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$1 }')"; \ - section="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$(NF - 2) }')"; \ + addr="$$$$(echo "$$$$sym_line" | awk '{ print $$$$1 }')"; \ + section="$$$$(echo "$$$$sym_line" | awk '{ print $$$$(NF - 2) }')"; \ objcopy_wrap_flags="$$$$objcopy_wrap_flags --add-symbol __real_$$$${sym}=$$$${section}:0x$$$${addr},function,global"; \ fi \ done ; \ diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 7a7ab1d..cbaf2c2 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -156,10 +156,11 @@ -MF $$(basename $$(a)).d -MT $$@ -c $$< -o $$@.orig objcopy_wrap_flags=''; \ for sym in $$($(1)-mocks); do \ - sym_line="$$$$($(OBJDUMP) -t $$@.orig | grep -E "[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s$$$$sym$$$$")"; \ + sym_line="$$$$($(OBJDUMP) -t $$@.orig \ + | grep -E "[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s$$$$sym$$$$")"; \ if [ ! -z "$$$$sym_line" ] ; then \ - addr="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$1 }')"; \ - section="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$(NF - 2) }')"; \ + addr="$$$$(echo "$$$$sym_line" | awk '{ print $$$$1 }')"; \ + section="$$$$(echo "$$$$sym_line" | awk '{ print $$$$(NF - 2) }')"; \ objcopy_wrap_flags="$$$$objcopy_wrap_flags --add-symbol __real_$$$${sym}=$$$${section}:0x$$$${addr},function,global"; \ fi \ done ; \ -- To view, visit https://review.coreboot.org/c/coreboot/+/59858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6023515191d6c236bf57870159a35d518f25e9d8 Gerrit-Change-Number: 59858 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/postcar: Set up postcar in C code
by Arthur Heymans (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Arthur Heymans, Aaron Durbin. Hello build bot (Jenkins), Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54299 to look at the new patch set (#6). Change subject: arch/x86/postcar: Set up postcar in C code ...................................................................... arch/x86/postcar: Set up postcar in C code TESTED on Qemu. Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/exit_car.S M src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/mtrr/earlymtrr.c M src/include/cpu/x86/mtrr.h 7 files changed, 64 insertions(+), 221 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/54299/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/54299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Gerrit-Change-Number: 54299 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86/postcar: Use a separate stack for C execution
by Arthur Heymans (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Lee Leahy, Huang Jin, Patrick Rudolph, Aaron Durbin. Hello build bot (Jenkins), Lee Leahy, Huang Jin, Patrick Rudolph, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54298 to look at the new patch set (#5). Change subject: arch/x86/postcar: Use a separate stack for C execution ...................................................................... arch/x86/postcar: Use a separate stack for C execution Add a stack in .bss for C execution. This will make it easier to move the setup of MTRRs in C code. Change-Id: I67cbc988051036b1a0519cec9ed614acede31fd7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/exit_car.S M src/drivers/intel/fsp1_1/exit_car.S M src/soc/intel/common/block/cpu/car/exit_car_fsp.S 3 files changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/54298/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/54298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67cbc988051036b1a0519cec9ed614acede31fd7 Gerrit-Change-Number: 54298 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/redrix: Swap TPM I2C with touchscreen I2C
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59863 ) Change subject: mb/google/brya/var/redrix: Swap TPM I2C with touchscreen I2C ...................................................................... mb/google/brya/var/redrix: Swap TPM I2C with touchscreen I2C According to the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:205648040 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I3a8339c23522019da884944246427512170510b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59863 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/redrix/gpio.c M src/mainboard/google/brya/variants/redrix/overridetree.cb 3 files changed, 37 insertions(+), 40 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b14178c..a658ce2 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -79,7 +79,8 @@ default 0x3 if BOARD_GOOGLE_PRIMUS4ES default 0x1 if BOARD_GOOGLE_GIMBLE default 0x3 if BOARD_GOOGLE_GIMBLE4ES - default 0x3 if BOARD_GOOGLE_REDRIX + default 0x1 if BOARD_GOOGLE_REDRIX + default 0x3 if BOARD_GOOGLE_REDRIX4ES default 0x1 if BOARD_GOOGLE_KANO default 0x3 if BOARD_GOOGLE_TAEKO default 0x1 if BOARD_GOOGLE_FELWINTER diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index afcb7e9..f9fd731 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -81,10 +81,10 @@ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 9531e5e..617ebc5 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -57,29 +57,25 @@ #+-------------------+---------------------------+ #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | | - #| I2C3 | cr50 TPM. Early init is | + #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | + #| I2C3 | TouchScreen | #| I2C5 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, - .i2c[5] = { + .i2c[3] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, }" device domain 0 on @@ -254,24 +250,10 @@ end end #I2C0 device ref i2c1 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN2513"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "300" - register "generic.reset_off_delay_ms" = "1" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "6" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_off_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x15 on end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end end end device ref i2c2 on @@ -388,10 +370,24 @@ end device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x15 on end end end device ref i2c5 on -- To view, visit https://review.coreboot.org/c/coreboot/+/59863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a8339c23522019da884944246427512170510b6 Gerrit-Change-Number: 59863 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratio
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59789 ) Change subject: soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratio ...................................................................... soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratio The patch refectors cpu_set_p_state_to_max_non_turbo_ratio(). The function is updated to use cpu_get_max_non_turbo_ratio(). TEST=Build the code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If73df17faaf7b870ae311460a868d52352683c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59789 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 2 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 617968a..27ff8cd 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -137,11 +137,10 @@ */ void cpu_set_p_state_to_max_non_turbo_ratio(void) { - msr_t msr, perf_ctl; + msr_t perf_ctl; /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; + perf_ctl.lo = (cpu_get_max_non_turbo_ratio() << 8) & 0xff00; perf_ctl.hi = 0; set_perf_control_msr(perf_ctl); -- To view, visit https://review.coreboot.org/c/coreboot/+/59789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If73df17faaf7b870ae311460a868d52352683c0c Gerrit-Change-Number: 59789 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add CPU related APIs
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59124 ) Change subject: soc/intel/common: Add CPU related APIs ...................................................................... soc/intel/common: Add CPU related APIs The patch defines below APIs : cpu_is_hybrid_supported() : Check whether CPU is hybrid CPU or not. cpu_get_bus_frequency() : Get CPU's bus frequency in MHz cpu_get_max_non_turbo_ratio() : Get CPU's max non-turbo ratio cpu_get_cpu_type() : Get CPU type. The function must be called if executing CPU is hybrid. TEST=Verified the APIs on the Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I680f43952ab4abce6e342206688ad32814970a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59124 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 2 files changed, 68 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 9372513..617968a 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -31,6 +31,13 @@ #define CPUID_CPU_TOPOLOGY_CORE_BITS(res, threadbits) \ ((CPUID_CPU_TOPOLOGY(LEVEL_BITS, (res).eax)) - threadbits) +#define CPUID_PROCESSOR_FREQUENCY 0X16 +#define CPUID_HYBRID_INFORMATION 0x1a + +/* Structured Extended Feature Flags */ +#define CPUID_STRUCT_EXTENDED_FEATURE_FLAGS 0x7 +#define HYBRID_FEATURE BIT(15) + /* * Set PERF_CTL MSR (0x199) P_Req with * Turbo Ratio which is the Maximum Ratio. @@ -185,6 +192,40 @@ return burst_state; } +bool cpu_is_hybrid_supported(void) +{ + struct cpuid_result cpuid_regs; + + /* CPUID.(EAX=07H, ECX=00H):EDX[15] indicates CPU is hybrid CPU or not*/ + cpuid_regs = cpuid_ext(CPUID_STRUCT_EXTENDED_FEATURE_FLAGS, 0); + return !!(cpuid_regs.edx & HYBRID_FEATURE); +} + +/* + * The function must be called if CPU is hybrid. If CPU is hybrid, the CPU type + * information is available in the Hybrid Information Enumeration Leaf(EAX=0x1A, ECX=0). + */ +uint8_t cpu_get_cpu_type(void) +{ + union cpuid_nat_model_id_and_core_type { + struct { + u32 native_mode_id:24; + u32 core_type:8; + } bits; + u32 hybrid_info; + }; + union cpuid_nat_model_id_and_core_type eax; + + eax.hybrid_info = cpuid_eax(CPUID_HYBRID_INFORMATION); + return (u8)eax.bits.core_type; +} + +/* It gets CPU bus frequency in MHz */ +uint32_t cpu_get_bus_frequency(void) +{ + return cpuid_ecx(CPUID_PROCESSOR_FREQUENCY); +} + /* * Program CPU Burst mode * true = Enable Burst mode. @@ -275,6 +316,18 @@ return ratio_max; } +uint8_t cpu_get_max_non_turbo_ratio(void) +{ + msr_t msr; + + /* + * PLATFORM_INFO(0xCE) MSR Bits[15:8] tells + * MAX_NON_TURBO_LIM_RATIO + */ + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.lo >> 8) & 0xff); +} + void configure_tcc_thermal_target(void) { const config_t *conf = config_of_soc(); diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 7e3deb0..094aceb 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -11,6 +11,21 @@ */ void cpu_set_max_ratio(void); +/* Get CPU bus frequency in MHz */ +u32 cpu_get_bus_frequency(void); + +/* Get CPU's max non-turbo ratio */ +u8 cpu_get_max_non_turbo_ratio(void); + +/* Check if CPU is hybrid CPU or not */ +bool cpu_is_hybrid_supported(void); + +/* + * Returns type of CPU that executing the function. It returns 0x20 + * if CPU is atom, otherwise 0x40 if CPU is CORE. The API must be called + * if CPU is hybrid. + */ +uint8_t cpu_get_cpu_type(void); /* * Get the TDP Nominal Ratio from MSR 0x648 Bits 7:0. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I680f43952ab4abce6e342206688ad32814970a91 Gerrit-Change-Number: 59124 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/var/gimble: Set PsysPmax to 143 W
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59797 ) Change subject: mb/var/gimble: Set PsysPmax to 143 W ...................................................................... mb/var/gimble: Set PsysPmax to 143 W This patch adds the setting of PsysPmax to 143 W according to gimble board design. BUG=b:206990759 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: Id6a203f05ecfcc1020a422850d35fa3fa64e01d0 Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59797 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ryan Lin <ryan.lin(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/gimble/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Ryan Lin: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 47e81d8..27ea5aa 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -32,6 +32,7 @@ register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" + register "PsysPmax" = "143" register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram -- To view, visit https://review.coreboot.org/c/coreboot/+/59797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6a203f05ecfcc1020a422850d35fa3fa64e01d0 Gerrit-Change-Number: 59797 Gerrit-PatchSet: 3 Gerrit-Owner: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59852 ) Change subject: soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h ...................................................................... soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h This enum is useful to have around for more than just the one file, so move it to a common header file, and while we're there, also add an option for UNKNOWN. TEST=boot test on brya0 Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59852 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 2 files changed, 11 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 2d63141..8959bf7 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -23,11 +23,6 @@ #define CPU_PCIE_BASE 0x40 -enum pcie_rp_type { - PCH_PCIE_RP, - CPU_PCIE_RP, -}; - enum vtd_base_index_type { VTD_GFX, VTD_IPU, @@ -40,11 +35,11 @@ static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number) { - assert(type == PCH_PCIE_RP || type == CPU_PCIE_RP); + assert(type == PCIE_RP_PCH || type == PCIE_RP_CPU); - if (type == PCH_PCIE_RP) + if (type == PCIE_RP_PCH) return rp_number; - else // type == CPU_PCIE_RP + else // type == PCIE_RP_CPU return CPU_PCIE_BASE + rp_number; } @@ -82,12 +77,12 @@ /* Configure PCH PCIE ports */ m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); - pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp, + pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCIE_RP_PCH, config->pch_pcie_rp, CONFIG_MAX_PCH_ROOT_PORTS); /* Configure CPU PCIE ports */ m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); - pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp, + pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, PCIE_RP_CPU, config->cpu_pcie_rp, CONFIG_MAX_CPU_ROOT_PORTS); } diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 8ed3e3d..f74706e 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -111,4 +111,10 @@ */ uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups); +enum pcie_rp_type { + PCIE_RP_UNKNOWN, + PCIE_RP_CPU, + PCIE_RP_PCH, +}; + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda Gerrit-Change-Number: 59852 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2021