coreboot-gerrit December 2021

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Change in coreboot[master]: acpi: Add #define for Mutex "no timeout" value
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59851 ) Change subject: acpi: Add #define for Mutex "no timeout" value ...................................................................... acpi: Add #define for Mutex "no timeout" value Some acpigen code may use mutexes, and it is a common idiom to pass a value for the Timeout field of 0xffff, which is interpreted by OSPM to mean "no timeout". Therefore add a macro for this value. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I16bc9f3f04dd1e3dc0f3eca3e56377e6f48132b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59851 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/acpi/acpigen.h 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 463c16d..c97713f 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -298,6 +298,8 @@ cppc_entry_t entries[CPPC_MAX_FIELDS_VER_3]; }; +#define ACPI_MUTEX_NO_TIMEOUT 0xffff + void acpigen_write_return_integer(uint64_t arg); void acpigen_write_return_namestr(const char *arg); void acpigen_write_return_string(const char *arg); 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16bc9f3f04dd1e3dc0f3eca3e56377e6f48132b2 Gerrit-Change-Number: 59851 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/felwinter: Correct garage wake event
by Patrick Georgi (Code Review) 06 Dec '21

06 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59861 ) Change subject: mb/google/brya/var/felwinter: Correct garage wake event ...................................................................... mb/google/brya/var/felwinter: Correct garage wake event Eject event is high. Set wake event to active high. The polarity of the SCI and the wakeup_event_action for the pen ejection feature were both backwards, and was causing the system to fail to enter sleep states because the event was always asserted. BUG=b:208937710 TEST=only release switch can wake system. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I568e9175c7a66599f7a525c32e4def7a79b55a0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59861 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/felwinter/gpio.c M src/mainboard/google/brya/variants/felwinter/overridetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/felwinter/gpio.c b/src/mainboard/google/brya/variants/felwinter/gpio.c index 4c07994..3f09d5b 100644 --- a/src/mainboard/google/brya/variants/felwinter/gpio.c +++ b/src/mainboard/google/brya/variants/felwinter/gpio.c @@ -10,7 +10,7 @@ /* A7 : SRCCLK_OE7# ==> PEN_DET_ODL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, NONE, DEEP), /* A8 : SRCCLKREQ7# ==> PEN_DET_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_A8, NONE, DEEP, EDGE_SINGLE), + PAD_CFG_GPI_SCI_HIGH(GPP_A8, NONE, DEEP, EDGE_SINGLE), /* B3 : PROC_GP2 ==> NC */ PAD_NC(GPP_B3, NONE), /* B5 : ISH_I2C0_SDA ==> NC */ diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 2cd5ad4..dafdbfc 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -264,7 +264,7 @@ register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A7)" register "key.wake_gpe" = "GPE0_DW0_08" register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I568e9175c7a66599f7a525c32e4def7a79b55a0a Gerrit-Change-Number: 59861 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: Kconfig: Fix BOOT_DEVICE_MEMORY_MAPPED
by Arthur Heymans (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54302 ) Change subject: Kconfig: Fix BOOT_DEVICE_MEMORY_MAPPED ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Not sure if this is needed anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/54302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c21e87d3375220a50645e0bf8b56fd23983f0c0 Gerrit-Change-Number: 54302 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Dec 2021 12:16:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cpu/car/exit_car_fsp.S: Align stack
by Arthur Heymans (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59914 ) Change subject: soc/intel/common/block/cpu/car/exit_car_fsp.S: Align stack ...................................................................... soc/intel/common/block/cpu/car/exit_car_fsp.S: Align stack Change-Id: I6b5864cfb9b013559cd318bc01733ba4d3792e65 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/exit_car_fsp.S 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/59914/1 diff --git a/src/soc/intel/common/block/cpu/car/exit_car_fsp.S b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S index fd79e8e..4b90628 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car_fsp.S +++ b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S @@ -18,6 +18,8 @@ /* Set up new stack. */ mov post_car_stack_top, %esp + /* Align the stack. */ + andl $0xfffffff0, %esp /* Call C code */ call main -- To view, visit https://review.coreboot.org/c/coreboot/+/59914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b5864cfb9b013559cd318bc01733ba4d3792e65 Gerrit-Change-Number: 59914 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]arch/x86: Tear down CAR in ramstage
by Arthur Heymans (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Raul Rangel, Jonathan Zhang, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Christian Walter, Morgan Jang, Tim Chu, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Anjaneya "Reddy" Chagam, Marshall Dawson, Jonathan Zhang, Johnny Lin, Morgan Jang, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54301 to look at the new patch set (#4). Change subject: [WIP]arch/x86: Tear down CAR in ramstage ...................................................................... [WIP]arch/x86: Tear down CAR in ramstage Postcar is a 'full' stage to just run a few instructions to disable CAR and setup MTRR for ramstage. This takes up a lot of place in ROM. This functionality can be moved into ramstage. Notes: Typically no caching is set up around cbmem so the LZMA compressed ramstage is being decompressed in uncached memory, which is likely to be slow. Change-Id: I02e5017ab2b6a6fd30b37edad19165c2531c8fd1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig M src/arch/x86/c_start.S M src/arch/x86/exit_car.S A src/arch/x86/exit_car.inc M src/arch/x86/postcar_loader.c M src/cpu/x86/mtrr/Makefile.inc M src/lib/program.ld M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.inc M src/soc/amd/common/block/cpu/car/Makefile.inc M src/soc/intel/common/block/cpu/Makefile.inc M src/soc/intel/xeon_sp/Kconfig 12 files changed, 56 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/54301/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/54301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02e5017ab2b6a6fd30b37edad19165c2531c8fd1 Gerrit-Change-Number: 54301 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/quark: Use common postcar MTRR setup
by Arthur Heymans (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54300 to look at the new patch set (#4). Change subject: soc/intel/quark: Use common postcar MTRR setup ...................................................................... soc/intel/quark: Use common postcar MTRR setup The common MTRR setup in postcar stage should now work for intel/quark. The only difference is in the implementation of rdmsr and wrmsr. Change-Id: I9fe9dc458383930a75d9459f77e347241d8b6f33 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/exit_car.S M src/include/cpu/x86/msr.h M src/soc/intel/quark/romstage/Makefile.inc D src/soc/intel/quark/romstage/mtrr.c 4 files changed, 0 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/54300/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/54300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fe9dc458383930a75d9459f77e347241d8b6f33 Gerrit-Change-Number: 54300 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86/postcar: Set up postcar in C code
by Arthur Heymans (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Arthur Heymans, Aaron Durbin. Hello build bot (Jenkins), Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54299 to look at the new patch set (#5). Change subject: arch/x86/postcar: Set up postcar in C code ...................................................................... arch/x86/postcar: Set up postcar in C code TESTED on Qemu. Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/exit_car.S M src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/mtrr/earlymtrr.c M src/include/cpu/x86/mtrr.h 7 files changed, 60 insertions(+), 219 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/54299/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/54299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Gerrit-Change-Number: 54299 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86/postcar: Use a separate stack for C execution
by Arthur Heymans (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Aaron Durbin. Hello build bot (Jenkins), Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54298 to look at the new patch set (#4). Change subject: arch/x86/postcar: Use a separate stack for C execution ...................................................................... arch/x86/postcar: Use a separate stack for C execution Add a stack in .bss for C execution. This will make it easier to move the setup of MTRRs in C code. Change-Id: I67cbc988051036b1a0519cec9ed614acede31fd7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/exit_car.S M src/drivers/intel/fsp1_1/exit_car.S M src/soc/intel/common/block/cpu/car/exit_car_fsp.S 3 files changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/54298/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/54298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67cbc988051036b1a0519cec9ed614acede31fd7 Gerrit-Change-Number: 54298 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/acer/g43t-am3: Add documentation
by Angel Pons (Code Review) 06 Dec '21

06 Dec '21

Attention is currently required from: Felix Singer, Paul Menzel, Michael Büchler. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56838 ) Change subject: mb/acer/g43t-am3: Add documentation ...................................................................... Patch Set 2: Code-Review+1 (4 comments) Patchset: PS2: Sorry, this fell off my radar. A nice way to ping reviewers of a change is to rebase it atop current master from time to time. File Documentation/mainboard/acer/g43t-am3.md: https://review.coreboot.org/c/coreboot/+/56838/comment/717be60c_c7e31e11 PS2, Line 105: `-c MX25L1605D/MX25L1608D/MX25L1673E` and `-c MX25L1605` should work. Hmmm, the block erasers defined in flashrom for these chips are incompatible: opcode 0x20 erases 64 KiB with `MX25L1605`, and 4 KiB with `MX25L1605D/MX25L1608D/MX25L1673E`. I'm pretty sure the latter is the correct definition, since Intel southbridges require flash chips to support 4 KiB erase granularity to use descriptor mode. https://review.coreboot.org/c/coreboot/+/56838/comment/6f0f5045_5ff87467 PS2, Line 108: flashrom -p internal -r backup.rom Huh, I would've expected the ME region to be unreadable internally. Have you modified the IFD? https://review.coreboot.org/c/coreboot/+/56838/comment/f464ac08_9d21c5ba PS2, Line 120: There : seems to be a diode that prevents you from powering the whole board with : your external programmer. I typically avoid using 2nd person (you, your) when writing documentation. Here I would rephrase this as follows: There seems to be a diode that prevents the external programmer from powering the whole board. Feel free to change this sentence or leave it as-is. -- To view, visit https://review.coreboot.org/c/coreboot/+/56838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e296b3efbff0260f32badc699f1062f9885fa53 Gerrit-Change-Number: 56838 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Comment-Date: Mon, 06 Dec 2021 11:49:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLER
by Subrata Banik (Code Review) 06 Dec '21

06 Dec '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59912 ) Change subject: cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLER ...................................................................... cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLER Fixes commit 29c7622 ("cpu/x86/mp_init.c: Fix building with no smihandler") broke SMM init because is_smm_enable() was called before smm_enable. Rework the code a little to make it clear what codepaths are used with CONFIG_HAVE_SMI_HANDLER. TESTED: now prodrive/hermes boots again. Change-Id: If4ce0dca2f29754d131dacf2da63e946be9a7b6d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59912 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/mp_init.c 1 file changed, 19 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 709e7a2..507b5fe 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1061,27 +1061,13 @@ return rmodule_memory_size(&smm_stub); } -static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) +static void fill_mp_state_smm(struct mp_state *state, const struct mp_ops *ops) { - /* - * Make copy of the ops so that defaults can be set in the non-const - * structure if needed. - */ - memcpy(&state->ops, ops, sizeof(*ops)); - - if (ops->get_cpu_count != NULL) - state->cpu_count = ops->get_cpu_count(); - - if (!is_smm_enabled()) - return; - if (ops->get_smm_info != NULL) ops->get_smm_info(&state->perm_smbase, &state->perm_smsize, - &state->smm_real_save_state_size); + &state->smm_real_save_state_size); - if (CONFIG(HAVE_SMI_HANDLER)) - state->smm_save_state_size = MAX(state->smm_real_save_state_size, - smm_stub_size()); + state->smm_save_state_size = MAX(state->smm_real_save_state_size, smm_stub_size()); /* * Make sure there is enough room for the SMM descriptor @@ -1095,11 +1081,25 @@ * Default to smm_initiate_relocation() if trigger callback isn't * provided. */ - if (CONFIG(HAVE_SMI_HANDLER) && - ops->per_cpu_smm_trigger == NULL) + if (ops->per_cpu_smm_trigger == NULL) mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation; } +static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) +{ + /* + * Make copy of the ops so that defaults can be set in the non-const + * structure if needed. + */ + memcpy(&state->ops, ops, sizeof(*ops)); + + if (ops->get_cpu_count != NULL) + state->cpu_count = ops->get_cpu_count(); + + if (CONFIG(HAVE_SMI_HANDLER)) + fill_mp_state_smm(state, ops); +} + static enum cb_err do_mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) { enum cb_err ret; 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4ce0dca2f29754d131dacf2da63e946be9a7b6d Gerrit-Change-Number: 59912 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-MessageType: merged

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coreboot-gerrit December 2021