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Hello build bot (Jenkins), Aaron Durbin,
I'd like you to reexamine a change. Please visit
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Change subject: arch/x86/postcar: Use a separate stack for C execution
......................................................................
arch/x86/postcar: Use a separate stack for C execution
Add a stack in .bss for C execution. This will make it easier to move
the setup of MTRRs in C code.
Change-Id: I67cbc988051036b1a0519cec9ed614acede31fd7
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/exit_car.S
M src/drivers/intel/fsp1_1/exit_car.S
M src/soc/intel/common/block/cpu/car/exit_car_fsp.S
3 files changed, 20 insertions(+), 2 deletions(-)
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Change subject: arch/x86/postcar: Set up postcar in C code
......................................................................
arch/x86/postcar: Set up postcar in C code
TESTED on Qemu.
Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/exit_car.S
M src/arch/x86/include/arch/romstage.h
M src/arch/x86/postcar.c
M src/arch/x86/postcar_loader.c
M src/cpu/x86/mtrr/Makefile.inc
M src/cpu/x86/mtrr/earlymtrr.c
M src/include/cpu/x86/mtrr.h
7 files changed, 60 insertions(+), 219 deletions(-)
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Change subject: soc/intel/quark: Use common postcar MTRR setup
......................................................................
soc/intel/quark: Use common postcar MTRR setup
The common MTRR setup in postcar stage should now work for
intel/quark. The only difference is in the implementation of rdmsr and
wrmsr.
Change-Id: I9fe9dc458383930a75d9459f77e347241d8b6f33
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/exit_car.S
M src/include/cpu/x86/msr.h
M src/soc/intel/quark/romstage/Makefile.inc
D src/soc/intel/quark/romstage/mtrr.c
4 files changed, 0 insertions(+), 109 deletions(-)
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Anjaneya "Reddy" Chagam, Marshall Dawson, Jonathan Zhang, Johnny Lin, Morgan Jang, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Felix Held,
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Change subject: [WIP]arch/x86: Tear down CAR in ramstage
......................................................................
[WIP]arch/x86: Tear down CAR in ramstage
Postcar is a 'full' stage to just run a few instructions to disable
CAR and setup MTRR for ramstage. This takes up a lot of place in ROM.
This functionality can be moved into ramstage.
Notes: Typically no caching is set up around cbmem so the LZMA
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Change-Id: I02e5017ab2b6a6fd30b37edad19165c2531c8fd1
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---
M src/arch/x86/Kconfig
M src/arch/x86/c_start.S
M src/arch/x86/exit_car.S
A src/arch/x86/exit_car.inc
M src/arch/x86/postcar_loader.c
M src/cpu/x86/mtrr/Makefile.inc
M src/lib/program.ld
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-i440fx/Makefile.inc
M src/soc/amd/common/block/cpu/car/Makefile.inc
M src/soc/intel/common/block/cpu/Makefile.inc
M src/soc/intel/xeon_sp/Kconfig
12 files changed, 56 insertions(+), 18 deletions(-)
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56838 )
Change subject: mb/acer/g43t-am3: Add documentation
......................................................................
Patch Set 2: Code-Review+1
(4 comments)
Patchset:
PS2:
Sorry, this fell off my radar. A nice way to ping reviewers of a change is to rebase it atop current master from time to time.
File Documentation/mainboard/acer/g43t-am3.md:
https://review.coreboot.org/c/coreboot/+/56838/comment/717be60c_c7e31e11
PS2, Line 105: `-c MX25L1605D/MX25L1608D/MX25L1673E` and `-c MX25L1605` should work.
Hmmm, the block erasers defined in flashrom for these chips are incompatible: opcode 0x20 erases 64 KiB with `MX25L1605`, and 4 KiB with `MX25L1605D/MX25L1608D/MX25L1673E`. I'm pretty sure the latter is the correct definition, since Intel southbridges require flash chips to support 4 KiB erase granularity to use descriptor mode.
https://review.coreboot.org/c/coreboot/+/56838/comment/6f0f5045_5ff87467
PS2, Line 108: flashrom -p internal -r backup.rom
Huh, I would've expected the ME region to be unreadable internally. Have you modified the IFD?
https://review.coreboot.org/c/coreboot/+/56838/comment/f464ac08_9d21c5ba
PS2, Line 120: There
: seems to be a diode that prevents you from powering the whole board with
: your external programmer.
I typically avoid using 2nd person (you, your) when writing documentation. Here I would rephrase this as follows:
There seems to be a diode that prevents the external programmer from powering the whole board.
Feel free to change this sentence or leave it as-is.
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59912 )
Change subject: cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLER
......................................................................
cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLER
Fixes commit 29c7622 ("cpu/x86/mp_init.c: Fix building with no
smihandler") broke SMM init because is_smm_enable() was called before
smm_enable.
Rework the code a little to make it clear what codepaths are used with
CONFIG_HAVE_SMI_HANDLER.
TESTED: now prodrive/hermes boots again.
Change-Id: If4ce0dca2f29754d131dacf2da63e946be9a7b6d
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59912
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Subrata Banik <subrata.banik(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/cpu/x86/mp_init.c
1 file changed, 19 insertions(+), 19 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Subrata Banik: Looks good to me, approved
Angel Pons: Looks good to me, approved
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 709e7a2..507b5fe 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -1061,27 +1061,13 @@
return rmodule_memory_size(&smm_stub);
}
-static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops)
+static void fill_mp_state_smm(struct mp_state *state, const struct mp_ops *ops)
{
- /*
- * Make copy of the ops so that defaults can be set in the non-const
- * structure if needed.
- */
- memcpy(&state->ops, ops, sizeof(*ops));
-
- if (ops->get_cpu_count != NULL)
- state->cpu_count = ops->get_cpu_count();
-
- if (!is_smm_enabled())
- return;
-
if (ops->get_smm_info != NULL)
ops->get_smm_info(&state->perm_smbase, &state->perm_smsize,
- &state->smm_real_save_state_size);
+ &state->smm_real_save_state_size);
- if (CONFIG(HAVE_SMI_HANDLER))
- state->smm_save_state_size = MAX(state->smm_real_save_state_size,
- smm_stub_size());
+ state->smm_save_state_size = MAX(state->smm_real_save_state_size, smm_stub_size());
/*
* Make sure there is enough room for the SMM descriptor
@@ -1095,11 +1081,25 @@
* Default to smm_initiate_relocation() if trigger callback isn't
* provided.
*/
- if (CONFIG(HAVE_SMI_HANDLER) &&
- ops->per_cpu_smm_trigger == NULL)
+ if (ops->per_cpu_smm_trigger == NULL)
mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation;
}
+static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops)
+{
+ /*
+ * Make copy of the ops so that defaults can be set in the non-const
+ * structure if needed.
+ */
+ memcpy(&state->ops, ops, sizeof(*ops));
+
+ if (ops->get_cpu_count != NULL)
+ state->cpu_count = ops->get_cpu_count();
+
+ if (CONFIG(HAVE_SMI_HANDLER))
+ fill_mp_state_smm(state, ops);
+}
+
static enum cb_err do_mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops)
{
enum cb_err ret;
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 )
Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
Patch Set 12: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59808/comment/abade7ab_9cf6c8f7
PS4, Line 12: TEST=Boot on PC Engines apu3
> Hmm, I retested with loglevel 0 and now the difference is 87 ms (1.7068686s − 1.620264s). Not as big of a difference but still an improvement.
thanks.
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Change subject: cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLER
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59912/comment/baa807b3_5b74a9b6
PS2, Line 9: 29c7622
> Commit 29c7622
Done
https://review.coreboot.org/c/coreboot/+/59912/comment/01d23080_4788e452
PS2, Line 16:
> Please add the tag: […]
Done
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Hello build bot (Jenkins), Paul Menzel, Subrata Banik, Angel Pons, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59912
to look at the new patch set (#4).
Change subject: cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLER
......................................................................
cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLER
Fixes commit 29c7622 ("cpu/x86/mp_init.c: Fix building with no
smihandler") broke SMM init because is_smm_enable() was called before
smm_enable.
Rework the code a little to make it clear what codepaths are used with
CONFIG_HAVE_SMI_HANDLER.
TESTED: now prodrive/hermes boots again.
Change-Id: If4ce0dca2f29754d131dacf2da63e946be9a7b6d
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/x86/mp_init.c
1 file changed, 19 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/59912/4
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