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Hello build bot (Jenkins), Michał Żygowski, Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59808
to look at the new patch set (#12).
Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
northbridge/amd/pi/00730F01: enable PARALLEL_MP
Disable LEGACY_SMP_INIT to enable PARALLEL_MP.
Also remove a large amount of APIC code that is now unnecessary.
TEST=Boot on PC Engines apu3
Boot time reduced from 1.707 seconds to 1.620 seconds average across
5 coldboots.
Inspired by CB:59693
Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/cpu/amd/pi/00730F01/model_16_init.c
M src/northbridge/amd/pi/00730F01/Kconfig
M src/northbridge/amd/pi/00730F01/northbridge.c
3 files changed, 27 insertions(+), 127 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59808/12
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Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 )
Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59808/comment/15a67a33_8dc94201
PS4, Line 12: TEST=Boot on PC Engines apu3
> > Yes, that's with the serial console enabled and with loglevel 7 […]
Hmm, I retested with loglevel 0 and now the difference is 87 ms (1.7068686s − 1.620264s). Not as big of a difference but still an improvement.
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Change subject: soc/mediatek: Add PCIe support
......................................................................
Patch Set 6:
(1 comment)
File src/soc/mediatek/common/pcie.c:
https://review.coreboot.org/c/coreboot/+/56791/comment/73398adf_bd162bc7
PS6, Line 111: mdelay(100);
> That’s pretty long for coreboot.
One way to avoid this delay would be to assert PERST# earlier, and do something else in the meantime. For instance, assert PERST# before memory init.
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Change subject: src/arch/x86/c_start.S: Add proper x86_64 code
......................................................................
Patch Set 2: Code-Review+1
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Change subject: src/arch/x86/exit_car: Add proper x86_64 code
......................................................................
Patch Set 2:
(1 comment)
File src/arch/x86/exit_car.S:
https://review.coreboot.org/c/coreboot/+/59873/comment/fedaf0c4_56185713
PS2, Line 112: #if CONFIG(SOC_SETS_MSRS)
:
: #if ENV_X86_64
: mov %rsp, %rbp
:
: /* Need to align stack to 16 bytes at the call instruction. Therefore
: account for the 1 push. */
: movq $0xfffffffffffffff0, %rax
: and %rax, %rsp
: mov %rbp, %rdi
: #else
: mov %esp, %ebp
: /* Need to align stack to 16 bytes at the call instruction. Therefore
: account for the 1 push. */
: andl $0xfffffff0, %esp
:
: sub $12, %esp
: push %ebp
: #endif
:
: call soc_set_mtrrs
: /* Ignore fixing up %esp since we're setting it a new value. */
:
: #if ENV_X86_64
: /* rax: new top_of_stack with setup_stack_and_mtrrs data removed */
: mov %rax, %rsp
: /* Align stack to 16 bytes at call instruction. */
: movq $0xfffffffffffffff0, %rax
: and %rax, %rsp
: #else
: /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */
: movl %eax, %esp
: /* Align stack to 16 bytes at call instruction. */
: andl $0xfffffff0, %esp
: #endif
: call soc_enable_mtrrs
: #else /* CONFIG_SOC_SETS_MSRS */
`soc/intel/quark` is the only user of `SOC_SETS_MSRS`, and Quark is 32-bit.
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Change subject: Documentation: Improve x86_64
......................................................................
Patch Set 8: Code-Review+1
(1 comment)
File Documentation/arch/x86/x86_64.md:
https://review.coreboot.org/c/coreboot/+/56017/comment/9e898900_8c02f6ef
PS8, Line 6: the PEI phase
Actually, `the SEC and PEI phases`
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Change subject: drivers/intel/usb4/retimer: Add function to correct EC port mapping
......................................................................
Patch Set 9:
(3 comments)
File src/drivers/intel/usb4/retimer/retimer.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134988):
https://review.coreboot.org/c/coreboot/+/59665/comment/1534c7b2_389a8b0c
PS9, Line 373: continue;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134988):
https://review.coreboot.org/c/coreboot/+/59665/comment/c48c4d90_6e15352a
PS9, Line 373: continue;
please, no space before tabs
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134988):
https://review.coreboot.org/c/coreboot/+/59665/comment/ffc819a0_b4d83732
PS9, Line 373: continue;
please, no spaces at the start of a line
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