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Change subject: soc/intel/alderlake: Implement function to map physical port to EC port
......................................................................
Patch Set 12:
(3 comments)
File src/soc/intel/alderlake/retimer.c:
https://review.coreboot.org/c/coreboot/+/59666/comment/90e9c3a6_9f8497dc
PS9, Line 30: die("Couldn't find correct port mapping or Invalid input port\n");
> I don't think we need to call die() here, returning some kind of error code is probably better (and […]
Ack
File src/soc/intel/alderlake/retimer.c:
https://review.coreboot.org/c/coreboot/+/59666/comment/e1070a3c_9542f88e
PS11, Line 21: printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", typec_port, ec_port);
> line over 96 characters
Please fix.
File src/soc/intel/alderlake/retimer.c:
https://review.coreboot.org/c/coreboot/+/59666/comment/ce431b6e_847940bd
PS12, Line 8: uint8_t
> so then maybe this should have a different return type
Ack
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Change subject: soc/intel/cse: config to enable oem key manifest
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59895/comment/26a1dcef_444adf8a
PS3, Line 13: ipu
> OEM KM has Audio FW's key hash. So,CSE uses this information to authenticate Audio FW. […]
Ack
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Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59836 )
Change subject: soc/intel/alderlake: Add support for ADL-N CPU Type
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/cpu.c:
PS3:
> For another patch: do we still need this function? Or should we rely on the Kconfigs, e.g. […]
For another patch: do we still need this function?
>> Which patch are referring here ?
To get LPM Mask for ADL-N, we are adding a case here in the function.
Other things would be taken care by the Kconfig
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Change subject: northbridge/amd/pi/00730F01/northbridge.c: remove unneded global variables
......................................................................
Patch Set 5: Code-Review+2
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Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59808/comment/c276ade2_42b8f05d
PS4, Line 12: TEST=Boot on PC Engines apu3
> Yes, that's with the serial console enabled and with loglevel 7
Hmm it could just be that the new code is just less verbose instead of actually faster. Could you try with serial console disabled?
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Change subject: soc/intel/cse: config to enable oem key manifest
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59895/comment/c5d38d49_6386dbc7
PS3, Line 13: ipu
OEM KM has Audio FW's key hash. So,CSE uses this information to authenticate Audio FW. The IPU is not dependent on OEM KM. Please update the commit with Kernel logs indicating audio authentication.
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Change subject: libpayload/libc/fmap: Implement new FlashMap API
......................................................................
Patch Set 4:
(1 comment)
File payloads/libpayload/include/fmap.h:
https://review.coreboot.org/c/coreboot/+/59494/comment/866d1eb0_7d194703
PS4, Line 6: #include <commonlib/bsd/cb_err.h>
Before using commonlib in exported headers, you'll also need to ensure that libpayload-using payloads can find it. We have multiple ways of using libpayload:
- a tree generated by "make install" needs to contain these files as a copy
- lpgcc can work both in such a tree and from a source tree with build/ and needs to figure out the right locations
Food for thought:
It _might_ be easier to make this more regular by copying commonlib headers into build/ somewhere (in a similar layout to what will be used in a "make install" tree) as an early build step and then just always use the same path.
It might be even easier to just copy all headers into build/ early so that the only difference between using build/ and using "make install" is the base directory.
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Change subject: soc/intel/cse: config to enable oem key manifest
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS4:
Please review the changes
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/59895/comment/767ace15_18724529
PS3, Line 184: Name OEM KM file
> name *of*
Ack
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Hello build bot (Jenkins), Tim Wawrzynczak, Sridhar Siricilla, Krishna P Bhat D, Patrick Rudolph, Ravindra N,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59895
to look at the new patch set (#4).
Change subject: soc/intel/cse: config to enable oem key manifest
......................................................................
soc/intel/cse: config to enable oem key manifest
CB change will enable the CSE region sub-partition OEMP,
where the OEMP binary will be stitched.
BUG=b:207820413
TEST: Boot to kernel and check for the ipu authentication
is successful
localhost ~ # dmesg | grep -i ipu
[ 9.206568] intel-ipu6 intel-ipu: IPU in secure mode
[ 9.218917] intel-ipu6 intel-ipu: IPC reset done
[ 9.226160] intel-ipu6 intel-ipu: cpd file name: intel/ipu6ep_fw.bin
[ 9.265134] intel-ipu6 intel-ipu: FW version: 20201224
[ 9.298977] intel-ipu6 intel-ipu: Sending BOOT_LOAD to CSE
[ 9.314555] intel-ipu6 intel-ipu: Sending AUTHENTICATE_RUN to CSE
[ 9.390078] intel-ipu6 intel-ipu: CSE authenticate_run done
[ 9.396530] intel-ipu6 intel-ipu: IPU driver version 1.0
Cq-Depend: chromium:3291463 config.baseboard.brya: config to support oem key manifest
| https://chromium-review.googlesource.com/c/chromiumos/overlays/chromiumos-o…
Signed-off-by: Ravindra N <ravindra(a)intel.corp-partner.google.com>
Change-Id: I3620adb2898efc002104e0ba8b2afd219c31f230
---
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/common/block/cse/Kconfig
2 files changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59895/4
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