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Change subject: [WIP]mb/prodrive/hermes: Fix BMC PCIe KVM
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60535/comment/8bad4cbb_8f03d7ae
PS1, Line 10: Clock
clock
https://review.coreboot.org/c/coreboot/+/60535/comment/6481a2d6_0589afcb
PS1, Line 11:
Are there different board revision available in public? So will this change cause regressions on older revisions?
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Change subject: soc/intel/alderlake: Add option to make MRC log silent
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60441/comment/49e2a706_68985481
PS3, Line 9: is default set to
defaults to
https://review.coreboot.org/c/coreboot/+/60441/comment/fecfc9b5_082ffb46
PS3, Line 10: Messages
messages
https://review.coreboot.org/c/coreboot/+/60441/comment/16f04c86_2133c972
PS3, Line 14: implemented `fsp_map_console_log_level()` that maps coreboot console
implement
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Hello Reka Norman, YH Lin, Tim Wawrzynczak, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60326
to look at the new patch set (#2).
Change subject: mb/google/brya: fix taniks' and vell's override.cb
......................................................................
mb/google/brya: fix taniks' and vell's override.cb
Taniks and vell were still using an older (and now obsolete) way
of defining the port numbers for the pmc_mux connectors.
Update taniks and vell to use new method of defining the ports.
BUG=b:212688966
TEST='emerge-brya coreboot chromeos-bootimage' and verify it builds
correctly.
Change-Id: Ie69a143ea2a43a1ee5a3c9f79975e1831e88c4b4
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brya/variants/taniks/overridetree.cb
M src/mainboard/google/brya/variants/vell/overridetree.cb
2 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/60326/2
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Change subject: mb/google/brya: fix taniks' and vell's override.cb
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
PING - brya build is currently broken until this merges.
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60443 )
Change subject: soc/intel/alderlake: Fix incorrect comment about debug consent
......................................................................
soc/intel/alderlake: Fix incorrect comment about debug consent
This patch makes the debug consent for ADL comment default value
comment proper. Default `Platform Debug Consent` value is
2: Enabled (Al probes and tracehub.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ic5eeb4f02d051dc1efba2deaecb51cbc7eac51f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60443
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---
M src/soc/intel/alderlake/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
EricR Lai: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 5419783..0c68351 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -307,7 +307,7 @@
config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
int "Debug Consent for ADL"
- # USB DBC is more common for developers so make this default to 3 if
+ # USB DBC is more common for developers so make this default to 2 if
# SOC_INTEL_DEBUG_CONSENT=y
default 2 if SOC_INTEL_DEBUG_CONSENT
default 0
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Change subject: soc/intel/common/cse: Helper API to know CSE SPI Protection Mode
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60403/comment/844100f8_596aec8c
PS3, Line 265: if (!hfs1.fields.mfg_mode)
> Kindly check now the added comment.
Ack
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Change subject: mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changed
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60442/comment/21562708_58c51593
PS4, Line 11: 1019 id changed to 10EC1019:0/10EC1019:1 from 10EC1019:1/10EC1019:2.
> Original code is referring to guybrush , using I2C 0x28, 0x29, 0x2a for 1019. […]
OK. Should uid="0" for 0x28 and uid="1" for 0x29?
File src/mainboard/google/guybrush/variants/dewatt/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/60442/comment/9e404241_0ba191d6
PS4, Line 151: register "uid" = "1"
> I refer to guybrush CRB codes, 0x29 w/o probed=1 and 0x2a with probed=1
Looks like the probed parameter was added in https://review.coreboot.org/c/coreboot/+/55028/3/src/mainboard/google/guybr…. I think probed is only required for peripherals that may not exist on the board. For dewatt these peripherals will always exist (right?), so we can remove probed from 0x2a as well.
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