coreboot-gerrit December 2021

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Change in coreboot[master]: device: Add definition for PCIe DVSEC ID
by Subrata Banik (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Francois Toguo Fotso, Tim Wawrzynczak, Karthik Ramasubramanian. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57803 ) Change subject: device: Add definition for PCIe DVSEC ID ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee09b2b46049f5484907a09ed5d132106c479db6 Gerrit-Change-Number: 57803 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 30 Dec 2021 13:50:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]mb/prodrive/hermes: Fix BMC PCIe KVM
by Arthur Heymans (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/60535 to review the following change. Change subject: [WIP]mb/prodrive/hermes: Fix BMC PCIe KVM ...................................................................... [WIP]mb/prodrive/hermes: Fix BMC PCIe KVM While some older schematics say the BMC uses PCIe clock source 6 it looks like newer board revisions actually use Clock source 0. TEST: See that a device is found under PCIe bridge 00.1d.6 and that KVM works in the BMC interface. Change-Id: Iecf6fba5c37cc5834dac8a4437e893ca76bb87dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/prodrive/hermes/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/60535/1 diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index db57382..6198eda 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -26,13 +26,13 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PcieClkSrcUsage[0]" = "20" # PCIe Slot1 + register "PcieClkSrcUsage[0]" = "14" # PCIe Slot1, also BMC on some revisions? register "PcieClkSrcUsage[1]" = "0x40" # PCIe Slot2 register "PcieClkSrcUsage[2]" = "0x42" # PCIe Slot4 register "PcieClkSrcUsage[3]" = "0x41" # PCIe Slot6 register "PcieClkSrcUsage[4]" = "8" # RP9 M2 Slot M x4 register "PcieClkSrcUsage[5]" = "15" # RP16 M2 Slot E x1 - register "PcieClkSrcUsage[6]" = "14" # BMC + register "PcieClkSrcUsage[6]" = "20" # BMC, PCIe slot1 on later revisions? register "PcieClkSrcUsage[7]" = "4" # PHY 3 register "PcieClkSrcUsage[8]" = "PCIE_CLK_RP0" # PCIe Slot3 register "PcieClkSrcUsage[9]" = "5" # PHY 4 -- To view, visit https://review.coreboot.org/c/coreboot/+/60535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecf6fba5c37cc5834dac8a4437e893ca76bb87dc Gerrit-Change-Number: 60535 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add option to make MRC log silent
by Nico Huber (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Felix Singer, Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Andrey Petrov, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60441 ) Change subject: soc/intel/alderlake: Add option to make MRC log silent ...................................................................... Patch Set 3: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60441/comment/3f26d91f_7aa08377 PS3, Line 16: HAVE_DEBUG_RAM_SETUP Actually, this commit should select HAVE_DEBUG_RAM_SETUP and then the user can enable DEBUG_RAM_SETUP. Patchset: PS2: > @Nico: Address your review comment here CB:60470 and CB:60471. […] Yes, very nice, thank you. And good call to move the mapping function to common code right away :) -- To view, visit https://review.coreboot.org/c/coreboot/+/60441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718 Gerrit-Change-Number: 60441 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 30 Dec 2021 12:56:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK
by build bot (Jenkins) (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Shelley Chen, Ravi kumar, Sudheer Amrabadi, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 ) Change subject: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK ...................................................................... Patch Set 101: Verified-1 (2 comments) File src/drivers/spi/spi_flash.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136635): https://review.coreboot.org/c/coreboot/+/50586/comment/089cb825_684c00d9 PS101, Line 533: while (1) suspect code indent for conditional statements (24, 24) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136635): https://review.coreboot.org/c/coreboot/+/50586/comment/8cba04cf_5e5af2d2 PS101, Line 554: while (1) suspect code indent for conditional statements (24, 24) -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 101 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <quic_c_sbhanu(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Thu, 30 Dec 2021 12:56:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp: Creates map between FSP and coreboot console level
by Nico Huber (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Andrey Petrov, Patrick Rudolph, EricR Lai. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60471 ) Change subject: drivers/intel/fsp: Creates map between FSP and coreboot console level ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60471/comment/82ca6aa6_578ff070 PS1, Line 12: Users to select HAVE_DEBUG_RAM_SETUP HAVE_DEBUG_RAM_SETUP is merely used to hide/show the user-selectable DEBUG_RAM_SETUP option. So it should be the caller of the mapping function that selects it, e.g. Callers have to select HAVE_DEBUG_RAM_SETUP config... Patchset: PS1: Looks nice :) -- To view, visit https://review.coreboot.org/c/coreboot/+/60471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I398d576fad68a0d0fc931c175bbc04fcbc2e54ec Gerrit-Change-Number: 60471 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 30 Dec 2021 12:54:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: console: Create helper function to get max console log level
by Nico Huber (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, EricR Lai. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60470 ) Change subject: console: Create helper function to get max console log level ...................................................................... Patch Set 1: Code-Review+1 (4 comments) Patchset: PS1: Thanks! Just two minor issues. File src/console/init.c: https://review.coreboot.org/c/coreboot/+/60470/comment/a725fc90_5fa5a967 PS1, Line 50: if (console_level == CONSOLE_LOG_NONE) : return BIOS_NEVER; This seems tricky. BIOS_NEVER is actually the highest (above SPEW) level. If you read get_max_console_log_level() as "give me the maximum allowed level", we'd actually say everything up to and including BIOS_NEVER is allowed. I guess we could drop this and let it run into the return 0 (or -1) at the end? https://review.coreboot.org/c/coreboot/+/60470/comment/62bbf1c1_a0275e58 PS1, Line 60: return 0; 0 is BIOS_EMERG. If we wanted to forbid all output (IMO valid on this fallback path), we could return -1. WDYT? File src/include/console/console.h: https://review.coreboot.org/c/coreboot/+/60470/comment/22dbed10_55479065 PS1, Line 67: static inline int console_log_level(int msg_level) { return 0; } We should have a similar dummy here. -- To view, visit https://review.coreboot.org/c/coreboot/+/60470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56349f22c71c9db757b2be8eeb2dbfe959f80397 Gerrit-Change-Number: 60470 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 30 Dec 2021 12:49:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Parse DDR Information through coreboot tables
by build bot (Jenkins) (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Sudheer Amrabadi, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 ) Change subject: libpayload: Parse DDR Information through coreboot tables ...................................................................... Patch Set 9: (1 comment) File payloads/libpayload/include/mem_chip_info.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136631): https://review.coreboot.org/c/coreboot/+/59193/comment/281e4b55_6bdbe23f PS9, Line 44: }dram_info; space required after that close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/59193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Gerrit-Change-Number: 59193 Gerrit-PatchSet: 9 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Thu, 30 Dec 2021 12:45:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secbo...
by build bot (Jenkins) (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Ravi kumar, Sudheer Amrabadi. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58545 ) Change subject: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. ...................................................................... Patch Set 14: (1 comment) File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136628): https://review.coreboot.org/c/coreboot/+/58545/comment/8e25bad5_6a2d30de PS14, Line 27: if (soc_modem_carve_out(&start, &end)) that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/58545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Gerrit-Change-Number: 58545 Gerrit-PatchSet: 14 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Thu, 30 Dec 2021 12:36:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz
by Nico Huber (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Henry Sun, Ren Kuo, Paul Menzel, Simon Yang, Angel Pons, Kane Chen, Karthik Ramasubramanian. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60301 ) Change subject: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz ...................................................................... Patch Set 10: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60301/comment/417f4202_95560d89 PS9, Line 12: per Intel recommendation > If Ren choice to change it by function mainboard_silicon_init_params() in ramstage.c, maybe I can drop my change first, and once FSP updated, I can go back here to update related header file, what do you think? It's already written, so let's just get it in. :) It would be nice to mention as much as possible about the FSP issue in the commit message. So if somebody else runs into this problem, they'd know what to do. -- To view, visit https://review.coreboot.org/c/coreboot/+/60301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Gerrit-Change-Number: 60301 Gerrit-PatchSet: 10 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 30 Dec 2021 12:23:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Simon Yang <simon1.yang(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config
by Nico Huber (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Jamie Chen, Henry Sun, Paul Menzel, Tim Wawrzynczak, Ren Kuo, Simon Yang, Angel Pons, Kane Chen, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 ) Change subject: soc/intel/jasperlake: Add CdClock frequency config ...................................................................... Patch Set 28: Code-Review+2 (2 comments) File src/soc/intel/jasperlake/chip.h: https://review.coreboot.org/c/coreboot/+/60009/comment/758b2f62_a2d95a68 PS28, Line 411: FSP will use the value to program clock frequency for core display if GOP : * is not run. Ex: the Chromebook normal mode. : * For the cases GOP is run, GOP will be in charge of the related register : * settings. This is a very nice comment. IMO, exactly the kind of information that the UPD comments in FSP headers always lack. (I've been pocking Intel to document the UPDs for years but they don't seem interested :-/ ) File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/60009/comment/be47b42a_b3f2bc82 PS21, Line 212: params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff; > sorry for missed the comment and thank you for your kindly remind. […] Looks done -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 28 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 30 Dec 2021 12:15:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Simon Yang <simon1.yang(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2021