coreboot-gerrit November 2021

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Change in coreboot[master]: mb/siemens/mc_ehl: Disable C-States for CPU and package
by Werner Zeh (Code Review) 03 Nov '21

03 Nov '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58893 ) Change subject: mb/siemens/mc_ehl: Disable C-States for CPU and package ...................................................................... mb/siemens/mc_ehl: Disable C-States for CPU and package Disable all C-states other than C0/C1 for CPU and package. Change-Id: I2c163f859dab4b0dc02896c70122e993cdd3db72 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/mainboard.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/58893/1 diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index e64dbda..eff2d21 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -10,6 +10,7 @@ #include <hwilib.h> #include <i210.h> #include <soc/gpio.h> +#include <soc/ramstage.h> #include <string.h> #include <timer.h> #include <timestamp.h> @@ -114,6 +115,15 @@ printk(BIOS_NOTICE, "done!\n"); } +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* Disable CPU power states (C-states) */ + params->Cx = 0; + + /* Set maximum package C-state to PkgC0C1 */ + params->PkgCStateLimit = 0; +} + static void mainboard_init(void *chip_info) { const struct pad_config *pads; -- To view, visit https://review.coreboot.org/c/coreboot/+/58893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c163f859dab4b0dc02896c70122e993cdd3db72 Gerrit-Change-Number: 58893 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/mc_ehl: Do not enable RAPL
by Werner Zeh (Code Review) 03 Nov '21

03 Nov '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58892 ) Change subject: mb/siemens/mc_ehl: Do not enable RAPL ...................................................................... mb/siemens/mc_ehl: Do not enable RAPL Do not enable Intel RAPL for all variants of mc_ehl in order to have a better real-time performance. Change-Id: I358e08acabb62a76f839531f613ddd0d03ac5f75 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/58892/1 diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig index 90881aa..d690b28 100644 --- a/src/mainboard/siemens/mc_ehl/Kconfig +++ b/src/mainboard/siemens/mc_ehl/Kconfig @@ -12,6 +12,7 @@ select MAINBOARD_HAS_LPC_TPM select TPM_MEASURED_BOOT select USE_SIEMENS_HWILIB + select INTEL_SKIP_SET_POWER_LIMITS source "src/mainboard/siemens/mc_ehl/variants/*/Kconfig" -- To view, visit https://review.coreboot.org/c/coreboot/+/58892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I358e08acabb62a76f839531f613ddd0d03ac5f75 Gerrit-Change-Number: 58892 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Fix CPU frequency if RAPL is disabled
by Werner Zeh (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Patrick Rudolph. Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58891 ) Change subject: soc/intel/elkhartlake: Fix CPU frequency if RAPL is disabled ...................................................................... soc/intel/elkhartlake: Fix CPU frequency if RAPL is disabled Set the CPU frequency to the maximum nun-turbo ratio if RAPL is not enabled. In addition disable turbo mode and EIST to get a stable CPU frequency under all circumstances to improve real-time performance. Change-Id: I30d09df45d2cb46ccaa2c7797392f2d2f43814da Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/elkhartlake/cpu.c 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/58891/1 diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 0fcc61d..39eca81 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -78,8 +78,16 @@ /* Set energy policy */ set_energy_perf_bias(ENERGY_POLICY_NORMAL); - /* Enable Turbo */ - enable_turbo(); + /* Set Max Non-Turbo ratio if RAPL is disabled. */ + if (CONFIG(INTEL_SKIP_SET_POWER_LIMITS)) { + cpu_set_p_state_to_max_non_turbo_ratio(); + /* Disable speed step and turbo mode */ + cpu_set_eist(false); + disable_turbo(); + } else { + /* Enable Turbo */ + enable_turbo(); + } } static void per_cpu_smm_trigger(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/58891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30d09df45d2cb46ccaa2c7797392f2d2f43814da Gerrit-Change-Number: 58891 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Skip RAPL programming if requested
by Werner Zeh (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Patrick Rudolph. Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58890 ) Change subject: soc/intel/elkhartlake: Skip RAPL programming if requested ...................................................................... soc/intel/elkhartlake: Skip RAPL programming if requested The Intel RAPL feature can have negative side effects on real-time performance. Use the Kconfig switch 'INTEL_SKIP_SET_POWER_LIMITS' to avoid that RAPL registers are programmed. This switch can be selected on mainboard level when needed. Change-Id: I51d94834ea8bec12a56b1cfc69fba275ad291bbc Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/elkhartlake/systemagent.c 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/58890/1 diff --git a/src/soc/intel/elkhartlake/systemagent.c b/src/soc/intel/elkhartlake/systemagent.c index aa9c87f..b497fda 100644 --- a/src/soc/intel/elkhartlake/systemagent.c +++ b/src/soc/intel/elkhartlake/systemagent.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <delay.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> @@ -55,8 +56,12 @@ /* Enable BIOS Reset CPL */ enable_bios_reset_cpl(); - mdelay(1); - config = config_of_soc(); - soc_config = &config->power_limits_config; - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + if (CONFIG(INTEL_SKIP_SET_POWER_LIMITS)) { + printk(BIOS_INFO, "Skip setting RAPL per configuration\n"); + } else { + mdelay(1); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/58890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d94834ea8bec12a56b1cfc69fba275ad291bbc Gerrit-Change-Number: 58890 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Decouple APL_SKIP_SET_POWER_LIMITS from Apollo Lake
by Werner Zeh (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58889 ) Change subject: soc/intel: Decouple APL_SKIP_SET_POWER_LIMITS from Apollo Lake ...................................................................... soc/intel: Decouple APL_SKIP_SET_POWER_LIMITS from Apollo Lake The Kconfig switch 'APL_SKIP_SET_POWER_LIMITS' was introduced on Apollo Lake to prevent the set up of the RAPL (Running Average Power Limit) registers and is furthermore used to program the maximum non-turbo CPU clock ratio. This is done in favor of a better real-time performance. This feature is now handy for other SoCs as well. To enable a wider usage of this feature decouple it from Apollo Lake and make it available for all Intel platforms. For a clean decoupling rename this switch to 'INTEL_SKIP_SET_POWER_LIMITS' and move it to src/soc/intel/Kconfig. Change-Id: Ib13e39e77c605b6e2a42aaac0c66cd7f75309ae0 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig M src/soc/intel/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c 8 files changed, 20 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/58889/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig index ae76f7b..6a1e77a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig @@ -8,7 +8,7 @@ select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + select INTEL_SKIP_SET_POWER_LIMITS select DRIVERS_I2C_PTN3460 endif # BOARD_SIEMENS_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig index d690157..24f9686 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig @@ -8,6 +8,6 @@ select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + select INTEL_SKIP_SET_POWER_LIMITS endif # BOARD_SIEMENS_MC_APL3 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index 877470f..b61b280 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -8,7 +8,7 @@ select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + select INTEL_SKIP_SET_POWER_LIMITS select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig index 812c4af..d789f78 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -8,7 +8,7 @@ select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + select INTEL_SKIP_SET_POWER_LIMITS select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index d519068..5bc8d91 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -38,3 +38,16 @@ than the one in non-topswap bootblock. This string will be passed onto ifittool (-A -n option). ifittool will not parse the region for MCU entries, and only locate the region and insert its address into FIT. + +config INTEL_SKIP_SET_POWER_LIMITS + bool + default n + help + In favor of a better real-time performance the CPU clock should be kept + as stable as possible. Since 'Running Average Power Limits (RAPL)' targets a + fixed TDP at the cost of a variable CPU clock this feature can have a negative + influence on the real-time performance. + Set this config option to skip the RAPL configuration and enable the maximum non-turbo + CPU clock ratio. + + diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 45e21dd..2be3a4e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -328,17 +328,9 @@ default 0xddffc000 depends on INTEL_LPSS_UART_FOR_CONSOLE -config APL_SKIP_SET_POWER_LIMITS - bool - default n - help - Some Apollo Lake mainboards do not need the Running Average Power - Limits (RAPL) algorithm for a constant power management. - Set this config option to skip the RAPL configuration. - config APL_SET_MIN_CLOCK_RATIO bool - depends on !APL_SKIP_SET_POWER_LIMITS + depends on !INTEL_SKIP_SET_POWER_LIMITS default n help If the power budget of the mainboard is limited, it can be useful to diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 651bd84..f1877a9 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -318,7 +318,7 @@ */ p2sb_unhide(); - if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { + if (CONFIG(INTEL_SKIP_SET_POWER_LIMITS)) { printk(BIOS_INFO, "Skip setting RAPL per configuration\n"); } else { config = config_of_soc(); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index af0a6dc..3713824 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -72,7 +72,7 @@ enable_pm_timer_emulation(); /* Set Max Non-Turbo ratio if RAPL is disabled. */ - if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { + if (CONFIG(INTEL_SKIP_SET_POWER_LIMITS)) { cpu_set_p_state_to_max_non_turbo_ratio(); /* Disable speed step */ cpu_set_eist(false); -- To view, visit https://review.coreboot.org/c/coreboot/+/58889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib13e39e77c605b6e2a42aaac0c66cd7f75309ae0 Gerrit-Change-Number: 58889 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Werner Zeh (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, Felix Held. Werner Zeh has uploaded a new patch set (#46) to the change originally created by Lean Sheng Tan. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... soc/intel/elkhartlake: Introduce Intel PSE The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and it's peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings which enables the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 156 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55367/46 -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 46 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/mc_ehl2: Clean up devicetree
by Mario Scheithauer (Code Review) 03 Nov '21

03 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58887 to look at the new patch set (#2). Change subject: mb/siemens/mc_ehl2: Clean up devicetree ...................................................................... mb/siemens/mc_ehl2: Clean up devicetree There are a bunch of devices in the devicetree that are disabled in FSP-S and not used on this board. Having them around in the devicetree, even if disabled, is not necessary and leads to a message in the log (left over static devices...check your devicetree). This commit cleans up devicetree.cb and removes all unused and disabled devices. Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 1 insertion(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/58887/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299 Gerrit-Change-Number: 58887 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/mc_eh2: Clean up devicetree
by Mario Scheithauer (Code Review) 03 Nov '21

03 Nov '21

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58887 ) Change subject: mb/siemens/mc_eh2: Clean up devicetree ...................................................................... mb/siemens/mc_eh2: Clean up devicetree There are a bunch of devices in the devicetree that are disabled in FSP-S and not used on this board. Having them around in the devicetree, even if disabled, is not necessary and leads to a message in the log (left over static devices...check your devicetree). This commit cleans up devicetree.cb and removes all unused and disabled devices. Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 1 insertion(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/58887/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 0ff38d7..47583e2 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -132,38 +132,10 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 08.0 off end # GNA - device pci 09.0 off end # CPU Intel Trace Hub - - device pci 10.0 off end # I2C6 - device pci 10.1 off end # I2C7 - device pci 10.5 on end # Integrated Error Handler - - device pci 11.0 off end # Intel PSE UART0 - device pci 11.1 off end # Intel PSE UART1 - device pci 11.2 off end # Intel PSE UART2 - device pci 11.3 off end # Intel PSE UART3 - device pci 11.4 off end # Intel PSE UART4 - device pci 11.5 off end # Intel PSE UART5 - device pci 11.6 off end # Intel PSE IS20 - device pci 11.7 off end # Intel PSE IS21 device pci 12.0 on end # GSPI2 - device pci 12.3 on end # Management Engine UMA Access - device pci 12.4 on end # Management Engine PTT DMA Controller - device pci 12.5 off end # UFS0 - device pci 12.7 off end # UFS1 - - device pci 13.0 off end # Intel PSE GSPI0 - device pci 13.1 off end # Intel PSE GSPI1 - device pci 13.2 off end # Intel PSE GSPI2 - device pci 13.3 off end # Intel PSE GSPI3 - device pci 13.4 off end # Intel PSE GPIO0 - device pci 13.5 off end # Intel PSE GPIO1 device pci 14.0 on end # USB3.1 xHCI - device pci 14.1 off end # USB3.1 xDCI (OTG) device pci 15.0 on end # I2C0 device pci 15.1 on end # I2C1 @@ -185,36 +157,16 @@ end device pci 15.3 on end # I2C3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 on end # Management Engine Interface 2 - device pci 16.4 on end # Management Engine Interface 3 - device pci 16.5 on end # Management Engine Interface 4 + device pci 16.0 hidden end # Management Engine Interface 1 device pci 17.0 on end # SATA - device pci 18.0 off end # Intel PSE I2C7 - device pci 18.1 off end # Intel PSE CAN0 - device pci 18.2 off end # Intel PSE CAN1 - device pci 18.3 off end # Intel PSE QEP0 - device pci 18.4 off end # Intel PSE QEP1 - device pci 18.5 off end # Intel PSE QEP2 - device pci 18.6 off end # Intel PSE QEP3 - device pci 19.0 on end # I2C4 device pci 19.1 on end # I2C5 device pci 19.2 on end # UART2 device pci 1a.0 on end # eMMC device pci 1a.1 on end # SD - device pci 1a.3 off end # Intel Safety Island - - device pci 1b.0 off end # Intel PSE I2C0 - device pci 1b.1 off end # Intel PSE I2C1 - device pci 1b.2 off end # Intel PSE I2C2 - device pci 1b.3 off end # Intel PSE I2C3 - device pci 1b.4 off end # Intel PSE I2C4 - device pci 1b.5 off end # Intel PSE I2C5 - device pci 1b.6 off end # Intel PSE I2C6 device pci 1c.0 on end # RP1 (pcie0 single VC) device pci 1c.1 on end # RP2 (pcie0 single VC) @@ -225,30 +177,18 @@ device pci 1d.0 off end # Intel PSE IPC (local host to PSE) device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0 device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1 - device pci 1d.3 off end # Intel PSE DMA0 - device pci 1d.4 off end # Intel PSE DMA1 - device pci 1d.5 off end # Intel PSE DMA2 - device pci 1d.6 off end # Intel PSE PWM - device pci 1d.7 off end # Intel PSE ADC device pci 1e.0 on end # UART0 device pci 1e.1 on end # UART1 - device pci 1e.2 off end # GSPI0 - device pci 1e.3 off end # GSPI1 device pci 1e.4 on end # PCH Time-Sensitive Networking GbE - device pci 1e.6 on end # HPET - device pci 1e.7 on end # IOAPIC device pci 1f.0 on # eSPI Interface chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.1 on end # P2SB device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 off end # Intel cAVS/HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI (flash & TPM) - device pci 1f.7 off end # PCH Intel Trace Hub end end -- To view, visit https://review.coreboot.org/c/coreboot/+/58887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299 Gerrit-Change-Number: 58887 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Some notes about how to integrate FSP
by Arthur Heymans (Code Review) 03 Nov '21

03 Nov '21

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58886 ) Change subject: Documentation: Some notes about how to integrate FSP ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Gerrit-Change-Number: 58886 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 03 Nov 2021 10:15:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Some notes about how to integrate FSP
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58886 ) Change subject: Documentation: Some notes about how to integrate FSP ...................................................................... Documentation: Some notes about how to integrate FSP While we don't _want_ FSP, we can't get around it sometimes. But when using it, we can still try to establish best practices to make life easier for everybody. Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/soc/intel/fsp/index.md 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/58886/1 diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 912c44b..48e644f 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -2,6 +2,19 @@ This section contains documentation about Intel-FSP in public domain. +## Integration Guidelines + +Some guiding principles when working on the glue to integrate FSP into coreboot, +e.g. on how to configure a board in devicetree when that has an effect on the +way FSP works: + +* It should be possible to replace FSP based boot with a native + coreboot implementation for a given chipset without touching the + mainboard code. +* The devicetree configures coreboot and part of what coreboot does + with the information is setting some FSP UPDs. The devicetree isn't + supposed to directly configure FSP. + ## Bugs As Intel doesn't even list known bugs, they are collected here until those are fixed. If possible a workaround is described here as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/58886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Gerrit-Change-Number: 58886 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021