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Change in coreboot[master]: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58640 ) Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC ...................................................................... soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC Add new folder and basic drivers for Mediatek SoC 'MT8186'. Difference of modules including in this patch between MT8186 and existing SoCs: Timer: Similar to MT8195, MT8186 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. TEST=boot from SPI-NOR and show uart log on MT8186 EVB BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58640 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/mediatek/mt8186/Kconfig A src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/bootblock.c A src/soc/mediatek/mt8186/emi.c A src/soc/mediatek/mt8186/include/soc/addressmap.h A src/soc/mediatek/mt8186/include/soc/emi.h A src/soc/mediatek/mt8186/include/soc/memlayout.ld A src/soc/mediatek/mt8186/include/soc/pll.h A src/soc/mediatek/mt8186/include/soc/spi.h A src/soc/mediatek/mt8186/include/soc/timer.h A src/soc/mediatek/mt8186/soc.c A src/soc/mediatek/mt8186/spi.c 12 files changed, 318 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig new file mode 100644 index 0000000..28589e3 --- /dev/null +++ b/src/soc/mediatek/mt8186/Kconfig @@ -0,0 +1,18 @@ +config SOC_MEDIATEK_MT8186 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select HAVE_UART_SPECIAL + +if SOC_MEDIATEK_MT8186 + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + +endif diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc new file mode 100644 index 0000000..c9cb305 --- /dev/null +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -0,0 +1,31 @@ +ifeq ($(CONFIG_SOC_MEDIATEK_MT8186),y) + +bootblock-y += bootblock.c +bootblock-y += ../common/mmu_operations.c +bootblock-$(CONFIG_SPI_FLASH) += spi.c +bootblock-y += ../common/timer.c +bootblock-y += ../common/uart.c + +verstage-$(CONFIG_SPI_FLASH) += spi.c +verstage-y += ../common/timer.c +verstage-y += ../common/uart.c + +romstage-y += ../common/cbmem.c +romstage-y += emi.c +romstage-$(CONFIG_SPI_FLASH) += spi.c +romstage-y += ../common/timer.c +romstage-y += ../common/uart.c + +ramstage-y += emi.c +ramstage-$(CONFIG_SPI_FLASH) += spi.c +ramstage-y += soc.c +ramstage-y += ../common/timer.c +ramstage-y += ../common/uart.c + +CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@ + +endif diff --git a/src/soc/mediatek/mt8186/bootblock.c b/src/soc/mediatek/mt8186/bootblock.c new file mode 100644 index 0000000..f48e78c --- /dev/null +++ b/src/soc/mediatek/mt8186/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu_operations.h> + +void bootblock_soc_init(void) +{ + mtk_mmu_init(); +} diff --git a/src/soc/mediatek/mt8186/emi.c b/src/soc/mediatek/mt8186/emi.c new file mode 100644 index 0000000..169b353 --- /dev/null +++ b/src/soc/mediatek/mt8186/emi.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 4.8 + */ + +#include <soc/emi.h> + +size_t sdram_size(void) +{ + return (size_t)4 * GiB; +} diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h new file mode 100644 index 0000000..20a48ad --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8186_INCLUDE_SOC_ADDRESSMAP_H__ +#define __SOC_MEDIATEK_MT8186_INCLUDE_SOC_ADDRESSMAP_H__ + +enum { + MCUSYS_BASE = 0x0C530000, + IO_PHYS = 0x10000000, +}; + +enum { + MCUCFG_BASE = MCUSYS_BASE + 0x00008000, +}; + +enum { + CKSYS_BASE = IO_PHYS + 0x00000000, + INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + IOCFG_LT_BASE = IO_PHYS + 0x00002000, + IOCFG_LM_BASE = IO_PHYS + 0x00002200, + IOCFG_LB_BASE = IO_PHYS + 0x00002400, + IOCFG_BL_BASE = IO_PHYS + 0x00002600, + IOCFG_RB_BASE = IO_PHYS + 0x00002A00, + IOCFG_RT_BASE = IO_PHYS + 0x00002C00, + GPIO_BASE = IO_PHYS + 0x00005000, + SPM_BASE = IO_PHYS + 0x00006000, + RGU_BASE = IO_PHYS + 0x00007000, + GPT_BASE = IO_PHYS + 0x00008000, + EINT_BASE = IO_PHYS + 0x0000B000, + APMIXED_BASE = IO_PHYS + 0x0000C000, + DEVAPC_AO_INFRA_PERI_BASE = IO_PHYS + 0x0000E000, + DEVAPC_AO_MM_BASE = IO_PHYS + 0x0000F000, + SYSTIMER_BASE = IO_PHYS + 0x00017000, + I2C0_DMA_BASE = IO_PHYS + 0x00200100, + I2C1_DMA_BASE = IO_PHYS + 0x00200200, + I2C2_DMA_BASE = IO_PHYS + 0x00200300, + I2C3_DMA_BASE = IO_PHYS + 0x00200480, + I2C4_DMA_BASE = IO_PHYS + 0x00200580, + I2C5_DMA_BASE = IO_PHYS + 0x00200700, + I2C6_DMA_BASE = IO_PHYS + 0x00200800, + I2C7_DMA_BASE = IO_PHYS + 0x00200900, + I2C8_DMA_BASE = IO_PHYS + 0x00200A80, + I2C9_DMA_BASE = IO_PHYS + 0x00200C00, + DEVAPC_BASE = IO_PHYS + 0x00207000, + EMI0_BASE = IO_PHYS + 0x00219000, + EMI0_MPU_BASE = IO_PHYS + 0x0021B000, + DRAMC_CHA_AO_BASE = IO_PHYS + 0x00220000, + SFLASH_REG_BASE = IO_PHYS + 0x01000000, + AUXADC_BASE = IO_PHYS + 0x01001000, + UART0_BASE = IO_PHYS + 0x01002000, + I2C7_BASE = IO_PHYS + 0x01004000, + I2C8_BASE = IO_PHYS + 0x01005000, + I2C0_BASE = IO_PHYS + 0x01007000, + I2C1_BASE = IO_PHYS + 0x01008000, + I2C2_BASE = IO_PHYS + 0x01009000, + SPI0_BASE = IO_PHYS + 0x0100A000, + I2C6_BASE = IO_PHYS + 0x0100D000, + I2C3_BASE = IO_PHYS + 0x0100F000, + SPI1_BASE = IO_PHYS + 0x01010000, + I2C4_BASE = IO_PHYS + 0x01011000, + SPI2_BASE = IO_PHYS + 0x01012000, + SPI3_BASE = IO_PHYS + 0x01013000, + SPI4_BASE = IO_PHYS + 0x01014000, + SPI5_BASE = IO_PHYS + 0x01015000, + I2C5_BASE = IO_PHYS + 0x01016000, + I2C9_BASE = IO_PHYS + 0x01019000, + SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00, + MSDC0_BASE = IO_PHYS + 0x01230000, + SSUSB_SIF_BASE = IO_PHYS + 0x01CA0000, + EFUSEC_BASE = IO_PHYS + 0x01CB0000, + MIPITX_BASE = IO_PHYS + 0x01CC0000, + MSDC0_TOP_BASE = IO_PHYS + 0x01CD0000, + SMI_BASE = IO_PHYS + 0x04002000, + SMI_LARB0 = IO_PHYS + 0x04003000, + DSI0_BASE = IO_PHYS + 0x04013000, +}; +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/emi.h b/src/soc/mediatek/mt8186/include/soc/emi.h new file mode 100644 index 0000000..decfa07 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/emi.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 4.8 + */ + +#ifndef SOC_MEDIATEK_MT8186_EMI_H +#define SOC_MEDIATEK_MT8186_EMI_H + +#include <stddef.h> + +size_t sdram_size(void); + +#endif /* SOC_MEDIATEK_MT8186_EMI_H */ diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld new file mode 100644 index 0000000..a1700e6 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. + * It will be returned before starting the ramstage. + * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. + */ +#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) +#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 64K) + +#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + +SECTIONS +{ + SRAM_START(0x00100000) + VBOOT2_WORK(0x00100000, 12K) + STACK(0x00103000, 8K) + TTB(0x00105000, 28K) + DMA_COHERENT(0x0010C000, 4K) + TPM_TCPA_LOG(0x0010D000, 2K) + FMAP_CACHE(0x0010D800, 2K) + WATCHDOG_TOMBSTONE(0x0010E000, 4) + CBFS_MCACHE(0x0010E004, 7K - 4) + TIMESTAMP(0x0010FC00, 1K) + /* MT8186 has 64KB SRAM. */ + SRAM_END(0x00110000) + + SRAM_L2C_START(0x00200000) + /* 4K reserved for BOOTROM until BOOTBLOCK is started */ + BOOTBLOCK(0x00201000, 60K) + /* + * The needed size can be obtained by: + * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz + */ + DRAM_INIT_CODE(0x00210000, 240K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0024c000, 272K) + PRERAM_CBFS_CACHE(0x00290000, 48K) + PRERAM_CBMEM_CONSOLE(0x0029C000, 400K) + SRAM_L2C_END(0x00300000) + + DRAM_START(0x40000000) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 2M) + RAMSTAGE(0x40300000, 256K) + + BL31(0x54600000, 0x60000) +} diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h new file mode 100644 index 0000000..0634a3b --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/pll.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.2 + */ + +#ifndef SOC_MEDIATEK_MT8186_PLL_H +#define SOC_MEDIATEK_MT8186_PLL_H + +#include <soc/pll_common.h> + +/* top_div rate */ +enum { + CLK26M_HZ = 26 * MHz, +}; + +/* top_mux rate */ +enum { + UART_HZ = CLK26M_HZ, +}; + +#endif /* SOC_MEDIATEK_MT8186_PLL_H */ diff --git a/src/soc/mediatek/mt8186/include/soc/spi.h b/src/soc/mediatek/mt8186/include/soc/spi.h new file mode 100644 index 0000000..cf64660 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/spi.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.6 + */ + +#ifndef MTK_MT8186_SPI_H +#define MTK_MT8186_SPI_H + +#include <spi-generic.h> + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/timer.h b/src/soc/mediatek/mt8186/include/soc/timer.h new file mode 100644 index 0000000..24d8529 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/timer.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.13 + */ + +#ifndef SOC_MEDIATEK_MT8186_TIMER_H +#define SOC_MEDIATEK_MT8186_TIMER_H + +#include <soc/timer_v2.h> + +#endif diff --git a/src/soc/mediatek/mt8186/soc.c b/src/soc/mediatek/mt8186/soc.c new file mode 100644 index 0000000..360893c --- /dev/null +++ b/src/soc/mediatek/mt8186/soc.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/emi.h> +#include <symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_mediatek_mt8186_ops = { + CHIP_NAME("SOC Mediatek MT8186") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c new file mode 100644 index 0000000..9504925 --- /dev/null +++ b/src/soc/mediatek/mt8186/spi.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.6, 5.8 + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/spi.h> + +static const struct spi_ctrlr spi_flash_ctrlr = { + .max_xfer_size = 65535, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_flash_ctrlr, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Gerrit-Change-Number: 58640 Gerrit-PatchSet: 10 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: move timer enum variables to timer_v2.h
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58829 ) Change subject: soc/mediatek/mt8195: move timer enum variables to timer_v2.h ...................................................................... soc/mediatek/mt8195: move timer enum variables to timer_v2.h Some enum variables of timer v2 are the same between MT8195 and MT8186, so we move them to common timer_v2.h. TEST=emerge-cherry coreboot BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I89891a19e622aa24783025e73c38c4ffa43aa166 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58829 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/timer_v2.h M src/soc/mediatek/mt8195/include/soc/timer.h 2 files changed, 13 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/include/soc/timer_v2.h b/src/soc/mediatek/common/include/soc/timer_v2.h index 507814b..2305928 100644 --- a/src/soc/mediatek/common/include/soc/timer_v2.h +++ b/src/soc/mediatek/common/include/soc/timer_v2.h @@ -9,6 +9,19 @@ #define GPT_MHZ 13 +enum { + TIE_0_EN = 1 << 3, + COMP_15_EN = 1 << 10, + COMP_20_EN = 1 << 11, + COMP_25_EN = 1 << 12, + + COMP_FEATURE_MASK = COMP_15_EN | COMP_20_EN | COMP_25_EN | TIE_0_EN, + + COMP_15_MASK = COMP_15_EN, + COMP_20_MASK = COMP_20_EN | TIE_0_EN, + COMP_25_MASK = COMP_20_EN | COMP_25_EN, +}; + struct mtk_gpt_regs { u32 reserved1[40]; u32 gpt6_con; diff --git a/src/soc/mediatek/mt8195/include/soc/timer.h b/src/soc/mediatek/mt8195/include/soc/timer.h index da073e1..d2959bf 100644 --- a/src/soc/mediatek/mt8195/include/soc/timer.h +++ b/src/soc/mediatek/mt8195/include/soc/timer.h @@ -5,16 +5,4 @@ #include <soc/timer_v2.h> -enum { - TIE_0_EN = 1 << 3, - COMP_15_EN = 1 << 10, - COMP_20_EN = 1 << 11, - COMP_25_EN = 1 << 12, - - COMP_FEATURE_MASK = COMP_15_EN | COMP_20_EN | COMP_25_EN | TIE_0_EN, - - COMP_15_MASK = COMP_15_EN, - COMP_20_MASK = COMP_20_EN | TIE_0_EN, - COMP_25_MASK = COMP_20_EN | COMP_25_EN, -}; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/58829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89891a19e622aa24783025e73c38c4ffa43aa166 Gerrit-Change-Number: 58829 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/amd: Always fetch CPU addr bits at runtime
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Arthur Heymans. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58686 ) Change subject: cpu/amd: Always fetch CPU addr bits at runtime ...................................................................... Patch Set 6: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58686/comment/dee6d31a_7b3b8706 PS4, Line 7: cpu > nit: CPU Done https://review.coreboot.org/c/coreboot/+/58686/comment/19314706_d18be08b PS4, Line 7: Allways > one `l` only: `Always` Done https://review.coreboot.org/c/coreboot/+/58686/comment/1d7c3d86_c5774edb PS4, Line 9: addr bits > Maybe `physical address size`? Done https://review.coreboot.org/c/coreboot/+/58686/comment/bf184641_078f59c9 PS4, Line 10: default > nit: value Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6f9234e091f44a2a03012e7e14c380aefbe717e Gerrit-Change-Number: 58686 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 03 Nov 2021 08:25:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: device/include: Fix potential build error
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58832 ) Change subject: device/include: Fix potential build error ...................................................................... device/include: Fix potential build error Add include guard for usbc_mux.h BUG=none BRANCH=none TEST=Build Pass Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: I47988edee84d17f0a15cfda1ac6f0187326bd331 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58832 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/include/device/usbc_mux.h 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/include/device/usbc_mux.h b/src/include/device/usbc_mux.h index e395d2d..0648a74 100644 --- a/src/include/device/usbc_mux.h +++ b/src/include/device/usbc_mux.h @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __USBC_MUX_H__ +#define __USBC_MUX_H__ + /* struct to hold all USB-C mux related variables */ struct usbc_mux_info { bool dp; /* DP connected */ @@ -67,3 +70,5 @@ }; const struct usbc_ops *usbc_get_ops(void); + +#endif /* __USBC_MUX_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47988edee84d17f0a15cfda1ac6f0187326bd331 Gerrit-Change-Number: 58832 Gerrit-PatchSet: 2 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: tests/Makefile: Remove ./ prefix when running tests
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58806 ) Change subject: tests/Makefile: Remove ./ prefix when running tests ...................................................................... tests/Makefile: Remove ./ prefix when running tests If ran with obj=/absolute path, then tests were failing to execute because the recipe tried running `.//absolutepath/...run`. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I9c3638b1af7531dbe8e956dcbe168250a235ead4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58806 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> --- M tests/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jakub Czapiga: Looks good to me, approved diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 6397e9b..7a7ab1d 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -232,7 +232,7 @@ $(alltests): $$($$(@)-bin) rm -f $(testobj)/junit-$(subst /,_,$(patsubst $(testobj)/%/,%,$(dir $^)))$*$.xml rm -f $(testobj)/$(subst /,_,$^).failed - -./$^ || echo failed > $(testobj)/$(subst /,_,$^).failed + -$^ || echo failed > $(testobj)/$(subst /,_,$^).failed # Build a code coverage report by collecting all the gcov files into a single # report. If COV is not set, this might be a user error, and they're trying -- To view, visit https://review.coreboot.org/c/coreboot/+/58806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c3638b1af7531dbe8e956dcbe168250a235ead4 Gerrit-Change-Number: 58806 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58740 ) Change subject: mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree ...................................................................... mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe devices. None of the used clock output is dedicated to a special device (CLK0 drives several devices on the mainboard, CLK1 and CLK2 are connected to a PCIe switch). Therefore do not use a port mapping of the clocks to avoid a stopping clock once a device is missing and the matching root port is disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free running clock. In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the value 0xFF to disable the CLKREQ-feature and unused clocks. Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58740 Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb 1 file changed, 12 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index f6ac8b7..e96e654 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -53,19 +53,19 @@ register "PcieRpEnable[3]" = "1" register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "0x00" - register "PcieClkSrcUsage[1]" = "0x01" - register "PcieClkSrcUsage[2]" = "0x02" - register "PcieClkSrcUsage[3]" = "0xFF" - register "PcieClkSrcUsage[4]" = "0xFF" - register "PcieClkSrcUsage[5]" = "0xFF" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcClkReq[0]" = "0xFF" - register "PcieClkSrcClkReq[1]" = "0xFF" - register "PcieClkSrcClkReq[2]" = "0xFF" - register "PcieClkSrcClkReq[3]" = "0xFF" - register "PcieClkSrcClkReq[4]" = "0xFF" - register "PcieClkSrcClkReq[5]" = "0xFF" + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" # Disable all L1 substates for PCIe root ports register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" -- To view, visit https://review.coreboot.org/c/coreboot/+/58740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf Gerrit-Change-Number: 58740 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amd/common/spi: Remove weak function
by Bao Zheng (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58844 to look at the new patch set (#4). Change subject: amd/common/spi: Remove weak function ...................................................................... amd/common/spi: Remove weak function Change-Id: I99509b6162f568c202cb82a8a238a895f6e93eb4 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/majolica/Makefile.inc M src/mainboard/amd/majolica/chromeos.c M src/mainboard/google/zork/Makefile.inc M src/mainboard/google/zork/chromeos.c M src/soc/amd/common/block/spi/fch_spi.c 5 files changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/58844/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99509b6162f568c202cb82a8a238a895f6e93eb4 Gerrit-Change-Number: 58844 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: Add unit-tests framework and first test case
by Jakub Czapiga (Code Review) 03 Nov '21

03 Nov '21

Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58242 ) Change subject: libpayload: Add unit-tests framework and first test case ...................................................................... Patch Set 7: (1 comment) File payloads/libpayload/tests/include/mocks/x86_io.h: https://review.coreboot.org/c/coreboot/+/58242/comment/f8006007_f1960f8d PS7, Line 28: void insb(int port, void *addr, unsigned long count); > Wouldn't it make more sense to add these to libpayload/include/mock/arch/io. […] It makes more sense, indeed. Please see: CL:58881 -- To view, visit https://review.coreboot.org/c/coreboot/+/58242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f Gerrit-Change-Number: 58242 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 03 Nov 2021 07:30:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Move x86 I/O functions to include/mock/arch/io.h
by Jakub Czapiga (Code Review) 03 Nov '21

03 Nov '21

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58881 ) Change subject: tests: Move x86 I/O functions to include/mock/arch/io.h ...................................................................... tests: Move x86 I/O functions to include/mock/arch/io.h Move th x86 I/O functions declarations from tests mocks to the mock architecture io.h. This will make x86 I/O-dependent tests simpler, because the x86_io.h from mocks will not have to be included manually. Change-Id: Ie7f06c992be306d2523f2079bc90adf114b93946 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M payloads/libpayload/include/mock/arch/io.h M payloads/libpayload/tests/drivers/Makefile.inc M payloads/libpayload/tests/drivers/speaker-test.c D payloads/libpayload/tests/include/mocks/x86_io.h 4 files changed, 17 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/58881/1 diff --git a/payloads/libpayload/include/mock/arch/io.h b/payloads/libpayload/include/mock/arch/io.h index 2bb6255..08c992f 100644 --- a/payloads/libpayload/include/mock/arch/io.h +++ b/payloads/libpayload/include/mock/arch/io.h @@ -26,4 +26,21 @@ void write32(volatile void *addr, uint32_t val); void write64(volatile void *addr, uint64_t val); +/* x86 I/O functions */ +unsigned int inl(int port); +unsigned short inw(int port); +unsigned char inb(int port); + +void outl(unsigned int val, int port); +void outw(unsigned short val, int port); +void outb(unsigned char val, int port); + +void outsl(int port, const void *addr, unsigned long count); +void outsw(int port, const void *addr, unsigned long count); +void outsb(int port, const void *addr, unsigned long count); + +void insl(int port, void *addr, unsigned long count); +void insw(int port, void *addr, unsigned long count); +void insb(int port, void *addr, unsigned long count); + #endif /* _ARCH_IO_H */ diff --git a/payloads/libpayload/tests/drivers/Makefile.inc b/payloads/libpayload/tests/drivers/Makefile.inc index e39921a..7705473 100644 --- a/payloads/libpayload/tests/drivers/Makefile.inc +++ b/payloads/libpayload/tests/drivers/Makefile.inc @@ -6,4 +6,3 @@ speaker-test-mocks += inb speaker-test-mocks += outb speaker-test-mocks += arch_ndelay -speaker-test-cflags += -include $(testsrc)/include/mocks/x86_io.h diff --git a/payloads/libpayload/tests/drivers/speaker-test.c b/payloads/libpayload/tests/drivers/speaker-test.c index 199fa58..a677fa4 100644 --- a/payloads/libpayload/tests/drivers/speaker-test.c +++ b/payloads/libpayload/tests/drivers/speaker-test.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <libpayload.h> -#include <mocks/x86_io.h> /* Include source to gain access to private defines */ #include "../drivers/speaker.c" diff --git a/payloads/libpayload/tests/include/mocks/x86_io.h b/payloads/libpayload/tests/include/mocks/x86_io.h deleted file mode 100644 index c35a572..0000000 --- a/payloads/libpayload/tests/include/mocks/x86_io.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef TESTS_MOCKS_X86_IO_H_ -#define TESTS_MOCKS_X86_IO_H_ - -unsigned int inl(int port); - -unsigned short inw(int port); - -unsigned char inb(int port); - -void outl(unsigned int val, int port); - -void outw(unsigned short val, int port); - -void outb(unsigned char val, int port); - -void outsl(int port, const void *addr, unsigned long count); - -void outsw(int port, const void *addr, unsigned long count); - -void outsb(int port, const void *addr, unsigned long count); - -void insl(int port, void *addr, unsigned long count); - -void insw(int port, void *addr, unsigned long count); - -void insb(int port, void *addr, unsigned long count); - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/58881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7f06c992be306d2523f2079bc90adf114b93946 Gerrit-Change-Number: 58881 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/redrix: Set RFI Spread Spectrum to 6%
by Chen Wisley (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, Wisley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58880 to look at the new patch set (#2). Change subject: mb/google/brya/var/redrix: Set RFI Spread Spectrum to 6% ...................................................................... mb/google/brya/var/redrix: Set RFI Spread Spectrum to 6% Set RFI Spread Spectrum to 6% for RF team request. BUG=b:200886627 TEST=build Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: Id0b42446e9e46ef629b5ca8d5d29faf2d771348d --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/58880/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b42446e9e46ef629b5ca8d5d29faf2d771348d Gerrit-Change-Number: 58880 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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