coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/alderlake: Enable Intel FIVR RFI settings
by Chen Wisley (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/58878 to review the following change. Change subject: soc/intel/alderlake: Enable Intel FIVR RFI settings ...................................................................... soc/intel/alderlake: Enable Intel FIVR RFI settings Add RFI UPD settings to mitigate RFI noise issues and exporting these UPDs to override via board devicetree. BUG=none TEST=build Change-Id: I37bfef295fcd886d4f01abd40f9467a0791e9e34 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/58878/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 699626b..3bdffd8 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -495,6 +495,22 @@ /* Platform Power Pmax */ uint16_t PsysPmax; + /* + * FivrRfiFrequency + * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. + * 0: Auto + * Range varies based on XTAL clock: + * 0-1918 (Up to 191.8HMz) for 24MHz clock + * 0-1535 (Up to 153.5MHz) for 19MHz clock + */ + uint16_t FivrRfiFrequency; + /* + * FivrSpreadSpectrum + * Set the Spread Spectrum Range. + * Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. Each Range is translated to an encoded value for FIVR register. + * 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. + */ + uint8_t FivrSpreadSpectrum; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 9ed8acd..fdd1fc6 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -731,6 +731,13 @@ config->ext_fivr_settings.vnn_icc_max_ma; } +static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ + s_cfg->FivrRfiFrequency = config->FivrRfiFrequency; + s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum; +} + static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, struct soc_intel_alderlake_config *config) { @@ -761,6 +768,7 @@ fill_fsps_misc_power_params, fill_fsps_irq_params, fill_fsps_fivr_params, + fill_fsps_fivr_rfi_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/58878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37bfef295fcd886d4f01abd40f9467a0791e9e34 Gerrit-Change-Number: 58878 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/kano: Update GPIO table for speak and dmic
by CT Lin (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Grace Kao, David Wu, Tim Wawrzynczak. CT Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58877 ) Change subject: mb/google/brya/var/kano: Update GPIO table for speak and dmic ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: After the test on kano, speaker and dmic can work normally. -- To view, visit https://review.coreboot.org/c/coreboot/+/58877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4 Gerrit-Change-Number: 58877 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: CT Lin <ctlin0(a)nuvoton.corp-partner.google.com> Gerrit-Reviewer: Grace Kao <grace.kao(a)intel.com> Gerrit-Reviewer: Grace Kao <grace.kao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Grace Kao <grace.kao(a)intel.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Grace Kao <grace.kao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Nov 2021 05:25:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl: Enable Row-Hammer prevention
by Werner Zeh (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58856 ) Change subject: mb/siemens/mc_ehl: Enable Row-Hammer prevention ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52f68525e882aee26822d9b3c488639c00f27d17 Gerrit-Change-Number: 58856 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 05:09:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl2: Configure SD card detect pin in devicetree
by Werner Zeh (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58855 ) Change subject: mb/siemens/mc_ehl2: Configure SD card detect pin in devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I708eb112fa054f2f88857001c409fb62493b6206 Gerrit-Change-Number: 58855 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 05:08:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetree
by Werner Zeh (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58853 ) Change subject: mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47e8528bea993ed527a0aecdbc93b94bbd9a7a49 Gerrit-Change-Number: 58853 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 05:08:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree
by Werner Zeh (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58852 ) Change subject: mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81419887b7f463a937917b971465245c1cb46b94 Gerrit-Change-Number: 58852 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 05:06:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: Update GPIO table for speak and dmic
by David Wu (Code Review) 03 Nov '21

03 Nov '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58877 ) Change subject: mb/google/brya/var/kano: Update GPIO table for speak and dmic ...................................................................... mb/google/brya/var/kano: Update GPIO table for speak and dmic Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1) Set GPIO GPP_S0 ~ GPP_S3 to NF4 and GPP_R6 ~ GPP_R7 to NF3. BUG=b:204844177 b:202913826 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4 --- M src/mainboard/google/brya/variants/kano/fw_config.c M src/mainboard/google/brya/variants/kano/gpio.c 2 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/58877/1 diff --git a/src/mainboard/google/brya/variants/kano/fw_config.c b/src/mainboard/google/brya/variants/kano/fw_config.c index 55a6fad..631a908 100644 --- a/src/mainboard/google/brya/variants/kano/fw_config.c +++ b/src/mainboard/google/brya/variants/kano/fw_config.c @@ -8,8 +8,8 @@ static const struct pad_config dmic_enable_pads[] = { PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* DMIC_DATA1_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ }; static const struct pad_config dmic_disable_pads[] = { @@ -24,10 +24,10 @@ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), /* I2S_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), /* I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */ }; static const struct pad_config i2s_disable_pads[] = { diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 6f40da1..898c87c 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -82,18 +82,18 @@ /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* GPD11: LANPHYC ==> NC */ PAD_NC(GPD11, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/58877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4 Gerrit-Change-Number: 58877 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush/bootblock: add comment on selecting eSPI interface
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58876 ) Change subject: mb/google/guybrush/bootblock: add comment on selecting eSPI interface ...................................................................... mb/google/guybrush/bootblock: add comment on selecting eSPI interface Setting the PM_ESPI_CS_USE_DATA2 bit in PM_SPI_PAD_PU_PD results in the eSPI transactions being sent via the SPI2 pins instead of the SPI1 pins. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb --- M src/mainboard/google/guybrush/bootblock.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/58876/1 diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 83ac43a..187b2ef 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -63,6 +63,7 @@ /* Early eSPI interface configuration */ + /* Use SPI2 pins for eSPI */ dword = pm_read32(PM_SPI_PAD_PU_PD); dword |= PM_ESPI_CS_USE_DATA2; pm_write32(PM_SPI_PAD_PU_PD, dword); -- To view, visit https://review.coreboot.org/c/coreboot/+/58876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb Gerrit-Change-Number: 58876 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/include/gpio: fix GPIO 106 native function names
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58874 to look at the new patch set (#3). Change subject: soc/amd/cezanne/include/gpio: fix GPIO 106 native function names ...................................................................... soc/amd/cezanne/include/gpio: fix GPIO 106 native function names The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed that the native function names don't have the EMMC_ prefix. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6 --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/soc/amd/cezanne/include/soc/gpio.h 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/58874/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6 Gerrit-Change-Number: 58874 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8195 Cherry review ToT
by Hung-Te Lin (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52260 ) Change subject: DO-NOT-SUBMIT: MT8195 Cherry review ToT ...................................................................... Patch Set 204: (1 comment) Patchset: PS204: oh you're right, it's yidi's change. well let's ignore it... -- To view, visit https://review.coreboot.org/c/coreboot/+/52260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 Gerrit-Change-Number: 52260 Gerrit-PatchSet: 204 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 03:35:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021