coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/cannonlake: Fix PEG1 _PRT generation
by Arthur Heymans (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Arthur Heymans has uploaded a new patch set (#4) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/58517 ) Change subject: soc/intel/cannonlake: Fix PEG1 _PRT generation ...................................................................... soc/intel/cannonlake: Fix PEG1 _PRT generation Some weird things happen inside FSP and the routing is not correctly applied, with PIN D being used but lacking a proper routing in ACPI. To work around this issue generate _PRT for all 4 INT pins. Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/58517/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51 Gerrit-Change-Number: 58517 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: tests: Move x86 I/O functions to include/mock/arch/io.h
by Yu-Ping Wu (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Jakub Czapiga, Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58881 ) Change subject: tests: Move x86 I/O functions to include/mock/arch/io.h ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7f06c992be306d2523f2079bc90adf114b93946 Gerrit-Change-Number: 58881 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Nov 2021 09:31:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add unit-tests framework and first test case
by Yu-Ping Wu (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Jakub Czapiga. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58242 ) Change subject: libpayload: Add unit-tests framework and first test case ...................................................................... Patch Set 7: (1 comment) File payloads/libpayload/tests/include/mocks/x86_io.h: https://review.coreboot.org/c/coreboot/+/58242/comment/7bf13ca5_98006cb9 PS7, Line 28: void insb(int port, void *addr, unsigned long count); > It makes more sense, indeed. […] CB:58881 -- To view, visit https://review.coreboot.org/c/coreboot/+/58242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f Gerrit-Change-Number: 58242 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 09:30:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add an overridable function for WDT clear status
by Yu-Ping Wu (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58834 ) Change subject: soc/mediatek: Add an overridable function for WDT clear status ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e Gerrit-Change-Number: 58834 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 09:20:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amd/lpc/espi: Remove weak function
by Bao Zheng (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58843 to look at the new patch set (#6). Change subject: amd/lpc/espi: Remove weak function ...................................................................... amd/lpc/espi: Remove weak function Change-Id: I39ae6405589d645eaa3e05759b1ffbd36e688d8f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/majolica/bootblock.c M src/mainboard/amd/mandolin/bootblock.c M src/mainboard/google/zork/bootblock.c M src/soc/amd/common/block/lpc/espi_util.c 4 files changed, 15 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/58843/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39ae6405589d645eaa3e05759b1ffbd36e688d8f Gerrit-Change-Number: 58843 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Arthur Heymans. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58689 ) Change subject: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58689/comment/3597dc1d_fbb179bf PS1, Line 9: this function is > nit: plural `these functions are` Done https://review.coreboot.org/c/coreboot/+/58689/comment/2e7660ad_ce5b3bbd PS1, Line 9: MTRR > nit: MTRRs Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Gerrit-Change-Number: 58689 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 03 Nov 2021 09:04:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/amd: Always fetch CPU addr bits at runtime
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58686 ) Change subject: cpu/amd: Always fetch CPU addr bits at runtime ...................................................................... cpu/amd: Always fetch CPU addr bits at runtime All supported AMD CPUs support getting the physical address size from cpuid so there is no need for a Kconfig default value. Change-Id: If6f9234e091f44a2a03012e7e14c380aefbe717e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58686 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/amd/mtrr/amd_mtrr.c 1 file changed, 2 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index fc3212f..8c703f5 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/device.h> #include <arch/cpu.h> +#include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -85,7 +86,6 @@ void amd_setup_mtrrs(void) { - unsigned long address_bits; unsigned long i; msr_t msr, sys_cfg; // Test if this CPU is a Fam 0Fh rev. F or later @@ -142,13 +142,6 @@ enable_cache(); - //K8 could be 40, and GH could be 48 - address_bits = CONFIG_CPU_ADDR_BITS; - - /* AMD specific cpuid function to query number of address bits */ - if (cpuid_eax(0x80000000) >= 0x80000008) - address_bits = cpuid_eax(0x80000008) & 0xff; - /* Now that I have mapped what is memory and what is not * Set up the mtrrs so we can cache the memory. */ @@ -156,5 +149,5 @@ // Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need // variable MTRR to span memory above 4GB // Lower revisions K8 need variable MTRR over 4GB - x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1); + x86_setup_var_mtrrs(cpu_phys_address_size(), has_tom2wb ? 0 : 1); } 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6f9234e091f44a2a03012e7e14c380aefbe717e Gerrit-Change-Number: 58686 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/redrix: Set RFI Spread Spectrum to 6%
by Chen Wisley (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Tim Wawrzynczak, Wisley Chen. Hello build bot (Jenkins), Tim Wawrzynczak, Wisley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58880 to look at the new patch set (#3). Change subject: mb/google/brya/var/redrix: Set RFI Spread Spectrum to 6% ...................................................................... mb/google/brya/var/redrix: Set RFI Spread Spectrum to 6% Set RFI Spread Spectrum to 6% for Redrix as RF team request. The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard as default. BUG=b:200886627 TEST=build Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: Id0b42446e9e46ef629b5ca8d5d29faf2d771348d --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/58880/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b42446e9e46ef629b5ca8d5d29faf2d771348d Gerrit-Change-Number: 58880 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/list: Add list_append
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58805 ) Change subject: lib/list: Add list_append ...................................................................... lib/list: Add list_append This method will add a node to the end of the list. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1792e40f789e3ef16ceca65ce4cae946e08583d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58805 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/include/list.h M src/lib/list.c M tests/lib/list-test.c 3 files changed, 30 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/include/list.h b/src/include/list.h index 6f0b54d..bfd92a7 100644 --- a/src/include/list.h +++ b/src/include/list.h @@ -15,6 +15,8 @@ void list_insert_after(struct list_node *node, struct list_node *after); // Insert list_node node before list_node before in a doubly linked list. void list_insert_before(struct list_node *node, struct list_node *before); +// Appends the node to the end of the list. +void list_append(struct list_node *node, struct list_node *head); #define list_for_each(ptr, head, member) \ for ((ptr) = container_of((head).next, typeof(*(ptr)), member); \ diff --git a/src/lib/list.c b/src/lib/list.c index 01d5c89..c3f8ee4 100644 --- a/src/lib/list.c +++ b/src/lib/list.c @@ -28,3 +28,11 @@ if (node->prev) node->prev->next = node; } + +void list_append(struct list_node *node, struct list_node *head) +{ + while (head->next) + head = head->next; + + list_insert_after(node, head); +} diff --git a/tests/lib/list-test.c b/tests/lib/list-test.c index 309346a..39bfb17 100644 --- a/tests/lib/list-test.c +++ b/tests/lib/list-test.c @@ -116,12 +116,32 @@ free(c1); } +void test_list_append(void **state) +{ + size_t idx; + struct test_container *node; + struct list_node root = {}; + struct test_container nodes[] = { + {1}, {2}, {3} + }; + + for (idx = 0; idx < ARRAY_SIZE(nodes); ++idx) + list_append(&nodes[idx].list_node, &root); + + idx = 0; + list_for_each(node, root, list_node) { + assert_ptr_equal(node, &nodes[idx]); + idx++; + } +} + int main(void) { const struct CMUnitTest tests[] = { cmocka_unit_test(test_list_insert_after), cmocka_unit_test(test_list_insert_before), cmocka_unit_test(test_list_remove), + cmocka_unit_test(test_list_append), }; 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1792e40f789e3ef16ceca65ce4cae946e08583d1 Gerrit-Change-Number: 58805 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/corsola: Add MediaTek MT8186 reference board
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58648 ) Change subject: mb/google/corsola: Add MediaTek MT8186 reference board ...................................................................... mb/google/corsola: Add MediaTek MT8186 reference board Add mainboard folder and drivers for new reference board 'Corsola'. TEST=build pass BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58648 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- A src/mainboard/google/corsola/Kconfig A src/mainboard/google/corsola/Kconfig.name A src/mainboard/google/corsola/Makefile.inc A src/mainboard/google/corsola/board_info.txt A src/mainboard/google/corsola/bootblock.c A src/mainboard/google/corsola/chromeos.c A src/mainboard/google/corsola/chromeos.fmd A src/mainboard/google/corsola/devicetree.cb A src/mainboard/google/corsola/mainboard.c A src/mainboard/google/corsola/memlayout.ld A src/mainboard/google/corsola/reset.c A src/mainboard/google/corsola/romstage.c 12 files changed, 161 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig new file mode 100644 index 0000000..8b38d2b --- /dev/null +++ b/src/mainboard/google/corsola/Kconfig @@ -0,0 +1,25 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Umbrella option to be selected by variant boards. +config BOARD_GOOGLE_CORSOLA_COMMON + def_bool n + +if BOARD_GOOGLE_CORSOLA_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_MEDIATEK_MT8186 + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select SPI_FLASH_INCLUDE_ALL_DRIVERS + +config MAINBOARD_DIR + string + default "google/corsola" + +config MAINBOARD_PART_NUMBER + string + default "Corsola" if BOARD_GOOGLE_CORSOLA +endif diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name new file mode 100644 index 0000000..3b44019 --- /dev/null +++ b/src/mainboard/google/corsola/Kconfig.name @@ -0,0 +1,5 @@ +comment "Corsola" + +config BOARD_GOOGLE_CORSOLA + bool "-> Corsola" + select BOARD_GOOGLE_CORSOLA_COMMON diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc new file mode 100644 index 0000000..4720dc5 --- /dev/null +++ b/src/mainboard/google/corsola/Makefile.inc @@ -0,0 +1,16 @@ +bootblock-y += memlayout.ld +bootblock-y += bootblock.c +bootblock-y += chromeos.c + +verstage-y += memlayout.ld +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += memlayout.ld +romstage-y += chromeos.c +romstage-y += romstage.c + +ramstage-y += memlayout.ld +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c diff --git a/src/mainboard/google/corsola/board_info.txt b/src/mainboard/google/corsola/board_info.txt new file mode 100644 index 0000000..3c37bdf --- /dev/null +++ b/src/mainboard/google/corsola/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Corsola MediaTek MT8186 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c new file mode 100644 index 0000000..99947c0 --- /dev/null +++ b/src/mainboard/google/corsola/bootblock.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/mmio.h> + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c new file mode 100644 index 0000000..3f0937f --- /dev/null +++ b/src/mainboard/google/corsola/chromeos.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + +} + +int get_recovery_mode_switch(void) +{ + /* TODO: use Chrome EC switches when EC support is added */ + return 0; +} diff --git a/src/mainboard/google/corsola/chromeos.fmd b/src/mainboard/google/corsola/chromeos.fmd new file mode 100644 index 0000000..7194632 --- /dev/null +++ b/src/mainboard/google/corsola/chromeos.fmd @@ -0,0 +1,45 @@ +# Firmware Layout Description for Chrome OS. +# +# The size and address of every section must be aligned to at least 4K, except: +# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. +# +# 'FMAP' may be found by binary search so its starting address should be better +# aligned to larger values. +# +# For sections to be preserved on update, add (PRESERVE) to individual sections +# instead of a group section; otherwise the preserved data may be wrong if you +# resize or reorder sections inside a group. + +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 32K # At least 16K. + } + RW_SECTION_A 1500K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + RW_MISC 36K { + RW_VPD(PRESERVE) 16K # At least 8K. + RW_NVRAM(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 8K + RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + } + RW_SECTION_B 1500K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 0x100 + } + RW_SHARED 36K { # Will be force updated on recovery. + SHARED_DATA 4K # 4K or less for netboot params. + RW_UNUSED + } + RW_LEGACY(CBFS) 1M # Minimal 1M. +} diff --git a/src/mainboard/google/corsola/devicetree.cb b/src/mainboard/google/corsola/devicetree.cb new file mode 100644 index 0000000..0c4bcb5 --- /dev/null +++ b/src/mainboard/google/corsola/devicetree.cb @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/mediatek/mt8186 + device cpu_cluster 0 on + device cpu 0 on end + end +end diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c new file mode 100644 index 0000000..e6040fa --- /dev/null +++ b/src/mainboard/google/corsola/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +static void mainboard_init(struct device *dev) +{ +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/corsola/memlayout.ld b/src/mainboard/google/corsola/memlayout.ld new file mode 100644 index 0000000..0f1fcec --- /dev/null +++ b/src/mainboard/google/corsola/memlayout.ld @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/corsola/reset.c b/src/mainboard/google/corsola/reset.c new file mode 100644 index 0000000..3a97ee5 --- /dev/null +++ b/src/mainboard/google/corsola/reset.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <reset.h> + +void do_board_reset(void) +{ +} diff --git a/src/mainboard/google/corsola/romstage.c b/src/mainboard/google/corsola/romstage.c new file mode 100644 index 0000000..891dc1b --- /dev/null +++ b/src/mainboard/google/corsola/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/stages.h> + +void platform_romstage_main(void) +{ +} 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6 Gerrit-Change-Number: 58648 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021