coreboot-gerrit November 2021

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Change in coreboot[master]: Documentation: Some notes about how to integrate FSP
by Arthur Heymans (Code Review) 03 Nov '21

03 Nov '21

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58886 ) Change subject: Documentation: Some notes about how to integrate FSP ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Gerrit-Change-Number: 58886 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 03 Nov 2021 10:15:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Some notes about how to integrate FSP
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58886 ) Change subject: Documentation: Some notes about how to integrate FSP ...................................................................... Documentation: Some notes about how to integrate FSP While we don't _want_ FSP, we can't get around it sometimes. But when using it, we can still try to establish best practices to make life easier for everybody. Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/soc/intel/fsp/index.md 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/58886/1 diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 912c44b..48e644f 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -2,6 +2,19 @@ This section contains documentation about Intel-FSP in public domain. +## Integration Guidelines + +Some guiding principles when working on the glue to integrate FSP into coreboot, +e.g. on how to configure a board in devicetree when that has an effect on the +way FSP works: + +* It should be possible to replace FSP based boot with a native + coreboot implementation for a given chipset without touching the + mainboard code. +* The devicetree configures coreboot and part of what coreboot does + with the information is setting some FSP UPDs. The devicetree isn't + supposed to directly configure FSP. + ## Bugs As Intel doesn't even list known bugs, they are collected here until those are fixed. If possible a workaround is described here as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/58886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Gerrit-Change-Number: 58886 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kukui: Add new config 'pico6' in coreboot
by Lucas Chen (Code Review) 03 Nov '21

03 Nov '21

Lucas Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58885 ) Change subject: mb/google/kukui: Add new config 'pico6' in coreboot ...................................................................... mb/google/kukui: Add new config 'pico6' in coreboot Add new board 'pico6' and set correct ram_id offset. BUG=b:204961721 TEST=None BRANCH=kukui Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Change-Id: I9413146913a38ed6a016b6b23ebd6c23040f4469 --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Kconfig.name 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/58885/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9413146913a38ed6a016b6b23ebd6c23040f4469 Gerrit-Change-Number: 58885 Gerrit-PatchSet: 2 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: Add unit-tests framework and first test case
by Jakub Czapiga (Code Review) 03 Nov '21

03 Nov '21

Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58242 ) Change subject: libpayload: Add unit-tests framework and first test case ...................................................................... Patch Set 7: (1 comment) File payloads/libpayload/tests/include/mocks/x86_io.h: https://review.coreboot.org/c/coreboot/+/58242/comment/027bcfe7_7a9633c6 PS7, Line 28: void insb(int port, void *addr, unsigned long count); > CB:58881 Oh, right. CB links to coreboot. Sorry. -- To view, visit https://review.coreboot.org/c/coreboot/+/58242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f Gerrit-Change-Number: 58242 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 03 Nov 2021 10:03:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/kukui: Add new config 'pico' in coreboot
by Lucas Chen (Code Review) 03 Nov '21

03 Nov '21

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58885 ) Change subject: mb/google/kukui: Add new config 'pico' in coreboot ...................................................................... mb/google/kukui: Add new config 'pico' in coreboot Add new board 'pico' and set correct ram_id offset. BUG=b:204961721 TEST=None BRANCH=kukui Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Change-Id: I9413146913a38ed6a016b6b23ebd6c23040f4469 --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Kconfig.name 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/58885/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 4c44c56..67f8c4e 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -74,6 +74,7 @@ default "Makomo" if BOARD_GOOGLE_MAKOMO default "Munna" if BOARD_GOOGLE_MUNNA default "Pico" if BOARD_GOOGLE_PICO + default "Pico6" if BOARD_GOOGLE_PICO6 config DRIVER_TPM_SPI_BUS hex @@ -91,7 +92,7 @@ hex default 0x10 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE || BOARD_GOOGLE_FENNEL || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN || BOARD_GOOGLE_MAKOMO || BOARD_GOOGLE_MUNNA default 0x20 if BOARD_GOOGLE_KAKADU || BOARD_GOOGLE_KATSU - default 0x30 if BOARD_GOOGLE_COZMO || BOARD_GOOGLE_PICO + default 0x30 if BOARD_GOOGLE_COZMO || BOARD_GOOGLE_PICO || BOARD_GOOGLE_PICO6 default 0x0 config BOARD_OVERRIDE_LCM_ID diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 3d5f309..7a533ef 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -81,3 +81,7 @@ config BOARD_GOOGLE_PICO bool "-> Pico" select BOARD_GOOGLE_JACUZZI_COMMON + +config BOARD_GOOGLE_PICO6 + bool "-> Pico6" + select BOARD_GOOGLE_JACUZZI_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/58885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9413146913a38ed6a016b6b23ebd6c23040f4469 Gerrit-Change-Number: 58885 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes: Configure pink rear vref based on eeprom
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Christian Walter, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58879 ) Change subject: mb/prodrive/hermes: Configure pink rear vref based on eeprom ...................................................................... Patch Set 1: Code-Review+1 (4 comments) File src/mainboard/prodrive/hermes/variants/r04/hda_verb.c: https://review.coreboot.org/c/coreboot/+/58879/comment/d171d708_273a1e66 PS1, Line 60: F nit: lowercase `f` https://review.coreboot.org/c/coreboot/+/58879/comment/bf75b8f0_23fab9ba PS1, Line 82: const u32 internal_config = get_internal_audio_cfg(board_cfg->internal_audio_connection); > line over 96 characters Please fix. Simply rename the constant to `internal_cfg`. https://review.coreboot.org/c/coreboot/+/58879/comment/1f5e009a_efc75053 PS1, Line 83: pink_config nit: Also rename this to `pink_cfg` for consistency. https://review.coreboot.org/c/coreboot/+/58879/comment/4631b1c6_bd0071a9 PS1, Line 89: get_port_c_vref_cfg(board_cfg->blue_rear_vref), Hmmm, this one is probably wrong then -- To view, visit https://review.coreboot.org/c/coreboot/+/58879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa11ba9c74f643e94046d4983fbce65dbedd1025 Gerrit-Change-Number: 58879 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 03 Nov 2021 09:46:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: disable PM ACPI timer if chosen
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58389 ) Change subject: soc/intel/xeon_sp: disable PM ACPI timer if chosen ...................................................................... soc/intel/xeon_sp: disable PM ACPI timer if chosen Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is disabled. This is done to bring SKL, CNL, DNV in line with the other platforms, in order to transition handling of the PM timer from FSP to coreboot in the follow-up changes. Disabling is done in `finalize` since FSP makes use of the PMtimer. Without PM Timer emulation disabling it too early would block. Change-Id: If85c64ba578991a1b112ceac7dd10276b58b0900 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58389 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lance Zhao --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/finalize.c M src/soc/intel/xeon_sp/include/soc/pmc.h 3 files changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lance Zhao: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index fa8403a..94fed02 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -36,6 +36,7 @@ select FSP_M_XIP select POSTCAR_STAGE select PARALLEL_MP_AP_WORK + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/xeon_sp/finalize.c b/src/soc/intel/xeon_sp/finalize.c index 044c1cc..76e3ef1 100644 --- a/src/soc/intel/xeon_sp/finalize.c +++ b/src/soc/intel/xeon_sp/finalize.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <intelpch/lockdown.h> #include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/util.h> #include "chip.h" @@ -26,6 +27,19 @@ { printk(BIOS_DEBUG, "Finalizing chipset.\n"); + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO. + * + * Note: In contrast to other platforms supporting PM timer emulation, + * disabling the PM timer must be done *after* FSP has run on Xeon-SP, + * because FSP makes use of the PM timer. + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); + apm_control(APM_CNT_FINALIZE); lock_pam0123(); diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index bbdb60b..69299b6 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -36,6 +36,8 @@ /* Memory mapped IO registers in PMC */ #define PMSYNC_TPR_CFG 0xc8 #define PMSYNC_LOCK (1 << 15) +#define PCH_PWRM_ACPI_TMR_CTL 0xfc +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x120 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4 * (x)) -- To view, visit https://review.coreboot.org/c/coreboot/+/58389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If85c64ba578991a1b112ceac7dd10276b58b0900 Gerrit-Change-Number: 58389 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Allow devicetree override to leave some VR setti...
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58807 ) Change subject: soc/intel/alderlake: Allow devicetree override to leave some VR settings as default ...................................................................... soc/intel/alderlake: Allow devicetree override to leave some VR settings as default Allow devicetree override to leave ac_loadline, dc_loadline and icc_max as default. Test=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I715345d5ea83aed9ee929b2a4e13921c9d8895b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58807 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/vr_config.c 1 file changed, 6 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 2180fc5..99caacb 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -87,9 +87,12 @@ if (chip_cfg->vr_config_enable) { cfg = chip_cfg; - s_cfg->AcLoadline[domain] = cfg->ac_loadline; - s_cfg->DcLoadline[domain] = cfg->dc_loadline; - s_cfg->IccMax[domain] = cfg->icc_max; + if (cfg->ac_loadline) + s_cfg->AcLoadline[domain] = cfg->ac_loadline; + if (cfg->dc_loadline) + s_cfg->DcLoadline[domain] = cfg->dc_loadline; + if (cfg->icc_max) + s_cfg->IccMax[domain] = cfg->icc_max; s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow; s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit; } else { -- To view, visit https://review.coreboot.org/c/coreboot/+/58807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I715345d5ea83aed9ee929b2a4e13921c9d8895b1 Gerrit-Change-Number: 58807 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Use dedicated VBT files for ADL-M
by Patrick Georgi (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Tim Wawrzynczak. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58202 ) Change subject: mb/intel/adlrvp: Use dedicated VBT files for ADL-M ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58202/comment/652e867c_f126bf48 PS3, Line 12: VBT files added at chrome-internal:4138272 So far the consensus seems to be that VBTs aren't in any way worthy of the amount of secrecy necessary. Since they're referred to here in public code, why not put them in the public repo, too? -- To view, visit https://review.coreboot.org/c/coreboot/+/58202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f Gerrit-Change-Number: 58202 Gerrit-PatchSet: 3 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 09:32:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Fix PEG1 _PRT generation
by Arthur Heymans (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Arthur Heymans has uploaded a new patch set (#5) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/58517 ) Change subject: soc/intel/cannonlake: Fix PEG1 _PRT generation ...................................................................... soc/intel/cannonlake: Fix PEG1 _PRT generation Some weird things happen inside FSP and the routing is not correctly applied, with PIN D being used but lacking a proper routing in ACPI. To work around this issue generate _PRT for all 4 INT pins. Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/58517/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/58517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51 Gerrit-Change-Number: 58517 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021