Attention is currently required from: Patrick Rudolph. Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58890 )
Change subject: soc/intel/elkhartlake: Skip RAPL programming if requested ......................................................................
soc/intel/elkhartlake: Skip RAPL programming if requested
The Intel RAPL feature can have negative side effects on real-time performance. Use the Kconfig switch 'INTEL_SKIP_SET_POWER_LIMITS' to avoid that RAPL registers are programmed. This switch can be selected on mainboard level when needed.
Change-Id: I51d94834ea8bec12a56b1cfc69fba275ad291bbc Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/soc/intel/elkhartlake/systemagent.c 1 file changed, 9 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/58890/1
diff --git a/src/soc/intel/elkhartlake/systemagent.c b/src/soc/intel/elkhartlake/systemagent.c index aa9c87f..b497fda 100644 --- a/src/soc/intel/elkhartlake/systemagent.c +++ b/src/soc/intel/elkhartlake/systemagent.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <delay.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> @@ -55,8 +56,12 @@ /* Enable BIOS Reset CPL */ enable_bios_reset_cpl();
- mdelay(1); - config = config_of_soc(); - soc_config = &config->power_limits_config; - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + if (CONFIG(INTEL_SKIP_SET_POWER_LIMITS)) { + printk(BIOS_INFO, "Skip setting RAPL per configuration\n"); + } else { + mdelay(1); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + } }