coreboot-gerrit November 2021

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Change in coreboot[master]: nb/intel/haswell/northbridge.c: Drop stale comment
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58922 ) Change subject: nb/intel/haswell/northbridge.c: Drop stale comment ...................................................................... nb/intel/haswell/northbridge.c: Drop stale comment This can now be controlled with the `MMCONF_BUS_NUMBER` Kconfig option. Change-Id: If0fdefc5b4339acc843443c551892b397ed39c2e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/northbridge.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/58922/1 diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 2322097..9ead46b 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -34,10 +34,6 @@ return NULL; } -/* - * TODO: We could determine how many PCIe buses we need in the bar. - * For now, that number is hardcoded to a max of 64. - */ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, -- To view, visit https://review.coreboot.org/c/coreboot/+/58922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0fdefc5b4339acc843443c551892b397ed39c2e Gerrit-Change-Number: 58922 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google,intel: Add missing include bootmode.h
by Kyösti Mälkki (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58921 ) Change subject: mb/google,intel: Add missing include bootmode.h ...................................................................... mb/google,intel: Add missing include bootmode.h Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/majolica/chromeos.c M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/brya/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/guybrush/chromeos.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/zork/chromeos.c M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/shadowmountain/chromeos.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/tglrvp/chromeos.c 31 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/58921/1 diff --git a/src/mainboard/amd/majolica/chromeos.c b/src/mainboard/amd/majolica/chromeos.c index c73e047..e5f3b5c 100644 --- a/src/mainboard/amd/majolica/chromeos.c +++ b/src/mainboard/amd/majolica/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index 1af2e02..630874c 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <console/console.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 50eeddc..2274ff7 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/chromeos.h> diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index add7346..e0a13b8 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index b88862c..14efdc3 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/mmio.h> #include <gpio.h> diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index fb904cc..0d75ac3 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index 9d3929e..dbdb273 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> #include <baseboard/gpio.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index d92ebb1..e3a9cd3 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 11931c6..73eae78 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index a74c2f7..a9456e4 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <baseboard/variants.h> diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 6a1f0b4..acd4cd6 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index df99e64..6cd48ea 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -3,6 +3,7 @@ #include <amdblocks/spi.h> #include <baseboard/gpio.h> #include <boardid.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index ee54ade..354d839 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index cf59636..5cfe9df 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index b85f976..a386dd6 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 03d3b4f..d0ceabc 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 5dd1e98..c9b91ad 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 94d76b9..a45ccdd 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index f49b639..3dc9f19 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index abd50c5..5f87821 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c index b581b90..cfb55a7 100644 --- a/src/mainboard/google/zork/chromeos.c +++ b/src/mainboard/google/zork/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index 244b942..85807a1 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 5fb7922..1e02e3d 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 5944406..7878a2a 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index c98c4f8..8a8bc42 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index c59fac8..320f92a 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index 270c84d..df01242 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/device.h> #include <gpio.h> diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 3b8725f..3a99e25 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c index 35a54a8..052191f 100644 --- a/src/mainboard/intel/shadowmountain/chromeos.c +++ b/src/mainboard/intel/shadowmountain/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index f01f7f1..c0ce968 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 7da61be..cb9af47 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/58921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Gerrit-Change-Number: 58921 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google: Fix indirect include bootmode.h
by Kyösti Mälkki (Code Review) 03 Nov '21

03 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58920 ) Change subject: mb/google: Fix indirect include bootmode.h ...................................................................... mb/google: Fix indirect include bootmode.h Change-Id: I882c567e6bca0982a0d3d44c742777c4d7bd5439 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/chromeos.c M src/mainboard/google/storm/chromeos.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_rialto/chromeos.c 6 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/58920/1 diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 38d12cb..4e744f1 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 4674581..2987e91 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boardid.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <console/console.h> #include <delay.h> @@ -9,7 +10,6 @@ #include <soc/cdp.h> #include <soc/blsp.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #define PP_SW 41 diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index 21cf94f..69f0fcc 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boardid.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <console/console.h> #include <delay.h> @@ -9,7 +10,6 @@ #include <soc/cdp.h> #include <soc/gsbi.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #define DEV_SW 15 #define REC_SW 16 diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index b99df04..cdea2ce 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "board.h" diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index a3ba752..a3fe3f4 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "board.h" diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 95158bf..7dcf7dc 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "board.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/58920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I882c567e6bca0982a0d3d44c742777c4d7bd5439 Gerrit-Change-Number: 58920 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC] ChromeOS: Promote variant_cros_gpio()
by Kyösti Mälkki (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58897 to look at the new patch set (#4). Change subject: [RFC] ChromeOS: Promote variant_cros_gpio() ...................................................................... [RFC] ChromeOS: Promote variant_cros_gpio() The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/majolica/chromeos.c M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/brya/chromeos.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/fizz/variants/baseboard/gpio.c M src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/glados/chromeos.c M src/mainboard/google/guybrush/chromeos.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/reef/variants/baseboard/gpio.c M src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/reef/variants/coral/gpio.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/chromeos.c M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/adlrvp/gpio.c M src/mainboard/intel/adlrvp/gpio_m.c M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/shadowmountain/chromeos.c M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c M src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c M src/vendorcode/google/chromeos/acpi.c M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/gnvs.c 84 files changed, 105 insertions(+), 313 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/58897/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Gerrit-Change-Number: 58897 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Set soc name for Stoneyridge
by Bao Zheng (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58555 ) Change subject: amdfwtool: Set soc name for Stoneyridge ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58555/comment/b4f67e97_f10875c5 PS4, Line 7: md > amd Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Gerrit-Change-Number: 58555 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Nov 2021 16:05:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Call the set_efs_table for Stoneyridge
by Bao Zheng (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge, Felix Held. Hello build bot (Jenkins), Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58871 to look at the new patch set (#3). Change subject: amdfwtool: Call the set_efs_table for Stoneyridge ...................................................................... amdfwtool: Call the set_efs_table for Stoneyridge Related to https://review.coreboot.org/c/coreboot/+/58555 Need to test if it works on Stoneyridge platform Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M util/amdfwtool/amdfwtool.c 2 files changed, 12 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/58871/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Gerrit-Change-Number: 58871 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Set soc name for Stoneyridge
by Bao Zheng (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge, Felix Held. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58555 to look at the new patch set (#5). Change subject: amdfwtool: Set soc name for Stoneyridge ...................................................................... amdfwtool: Set soc name for Stoneyridge For the stoneyridge, soc_name is not set in Makefile, so set_efs_table is not called. Keep it unchanged. Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M util/amdfwtool/amdfwtool.c 2 files changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/58555/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/58555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Gerrit-Change-Number: 58555 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/mp: Use unsigned type for CPU count
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Felix Held, Tim Chu. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58919 ) Change subject: cpu/x86/mp: Use unsigned type for CPU count ...................................................................... cpu/x86/mp: Use unsigned type for CPU count Retype the return value of the `get_cpu_count` function pointer and all related functions to `unsigned int`. Also retype the `cpu_count` member in `struct mp_state`. Change-Id: Ifb1e89a7e63952736503b0906dd11a6d38e9cc1c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/x86/mp_init.c M src/include/cpu/x86/mp.h M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.h M src/soc/amd/common/block/cpu/noncar/cpu.c M src/soc/amd/common/block/include/amdblocks/cpu.h M src/soc/amd/stoneyridge/cpu.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/cpu.h M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/util.c 21 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/58919/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index d4f3587..41a539f 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -585,7 +585,7 @@ configure_pch_power_sharing(); } -static int get_cpu_count(void) +static unsigned int get_cpu_count(void) { msr_t msr; unsigned int num_threads; diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index bc53214..95536ff 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -20,7 +20,7 @@ x86_mtrr_check(); } -static int get_cpu_count(void) +static unsigned int get_cpu_count(void) { const struct cpuid_result cpuid1 = cpuid(1); const unsigned int cores = (cpuid1.ebx >> 16) & 0xf; diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index e77f9aa..2dab60b 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -121,7 +121,7 @@ x86_mtrr_check(); } -static int get_cpu_count(void) +static unsigned int get_cpu_count(void) { msr_t msr; unsigned int num_threads; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 9de6b38..d28a690 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -377,7 +377,7 @@ x86_mtrr_check(); } -static int get_cpu_count(void) +static unsigned int get_cpu_count(void) { msr_t msr; unsigned int num_threads; diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c99732f..e4f3f08 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -671,7 +671,7 @@ struct mp_state { struct mp_ops ops; - int cpu_count; + unsigned int cpu_count; uintptr_t perm_smbase; size_t perm_smsize; /* Size of the real CPU save state */ diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 7ed82dd..85697d5 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -31,7 +31,7 @@ * need to be brought out of SIPI state as well as have SMM * handlers installed. */ - int (*get_cpu_count)(void); + unsigned int (*get_cpu_count)(void); /* * Optionally fill in permanent SMM region and save state size. If * this callback is not present no SMM handlers will be installed. diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 3206e4c..6ef30ab 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -128,7 +128,7 @@ return (uintptr_t)top; } -int fw_cfg_max_cpus(void) +unsigned int fw_cfg_max_cpus(void) { unsigned short max_cpus; diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h index e68ad97..f24d276 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h @@ -5,7 +5,7 @@ void fw_cfg_get(uint16_t entry, void *dst, int dstlen); int fw_cfg_check_file(FWCfgFile *file, const char *name); -int fw_cfg_max_cpus(void); +unsigned int fw_cfg_max_cpus(void); unsigned long fw_cfg_smbios_tables(int *handle, unsigned long *current); uintptr_t fw_cfg_tolud(void); diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index 98926bf..9550bb0 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -6,7 +6,7 @@ #include <cpu/amd/msr.h> #include <soc/iomap.h> -int get_cpu_count(void) +unsigned int get_cpu_count(void) { return 1 + (cpuid_ecx(0x80000008) & 0xff); } diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index 0627bc1..34ab0d3 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -3,7 +3,7 @@ #ifndef AMD_BLOCK_CPU_H #define AMD_BLOCK_CPU_H -int get_cpu_count(void); +unsigned int get_cpu_count(void); void set_cstate_io_addr(void); void write_resume_eip(void); diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 99b40a6..805a0de 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -37,7 +37,7 @@ x86_mtrr_check(); } -static int get_cpu_count(void) +static unsigned int get_cpu_count(void) { return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index af0a6dc..b8ab51b 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -160,7 +160,7 @@ } /* Find CPU topology */ -int get_cpu_count(void) +unsigned int get_cpu_count(void) { unsigned int num_virt_cores, num_phys_cores; diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 1dbc3d7..dc2e766 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -110,7 +110,7 @@ enable_turbo(); } -static int get_cpu_count(void) +static unsigned int get_cpu_count(void) { const struct pattrs *pattrs = pattrs_get(); diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 7c7a15d..403e10d 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -113,7 +113,7 @@ enable_turbo(); } -static int get_cpu_count(void) +static unsigned int get_cpu_count(void) { const struct pattrs *pattrs = pattrs_get(); diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index acd15a8..3b0dc8b 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -84,7 +84,7 @@ * MP Init callback function to Find CPU Topology. This function is common * among all SOCs and thus its in Common CPU block. */ -int get_cpu_count(void) +unsigned int get_cpu_count(void) { unsigned int num_virt_cores, num_phys_cores; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 8a413ea..d98cbca 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -11,7 +11,7 @@ * MP Init callback function to Find CPU Topology. This function is common * among all SOCs and thus its in Common CPU block. */ -int get_cpu_count(void); +unsigned int get_cpu_count(void); /* * MP Init callback function(get_microcode_info) to find the Microcode at diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 96eb79a..66a88de 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -197,7 +197,7 @@ } /* Find CPU topology */ -int get_cpu_count(void) +unsigned int get_cpu_count(void) { unsigned int num_cpus = detect_num_cpus_via_mch(); diff --git a/src/soc/intel/denverton_ns/include/soc/cpu.h b/src/soc/intel/denverton_ns/include/soc/cpu.h index a8af626..f97b151 100644 --- a/src/soc/intel/denverton_ns/include/soc/cpu.h +++ b/src/soc/intel/denverton_ns/include/soc/cpu.h @@ -5,7 +5,7 @@ #include <cpu/intel/cpu_ids.h> -int get_cpu_count(void); +unsigned int get_cpu_count(void); /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index ba417a7..d0968a8 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -165,7 +165,7 @@ x86_mtrr_check(); } -static int get_thread_count(void) +static unsigned int get_thread_count(void) { unsigned int num_phys = 0, num_virts = 0; diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 213735a..3027335 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -9,7 +9,7 @@ void unlock_pam_regions(void); uint8_t get_stack_busno(const uint8_t stack); msr_t read_msr_ppin(void); -int get_platform_thread_count(void); +unsigned int get_platform_thread_count(void); const IIO_UDS *get_iio_uds(void); unsigned int soc_get_num_cpus(void); void xeonsp_init_cpu_config(void); diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 4295704..9716ae4 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -81,7 +81,7 @@ return thread_count; } -int get_platform_thread_count(void) +unsigned int get_platform_thread_count(void) { return soc_get_num_cpus() * get_threads_per_package(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb1e89a7e63952736503b0906dd11a6d38e9cc1c Gerrit-Change-Number: 58919 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/qemu-i440fx: Refactor `fw_cfg_max_cpus()`
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58918 ) Change subject: mb/emulation/qemu-i440fx: Refactor `fw_cfg_max_cpus()` ...................................................................... mb/emulation/qemu-i440fx: Refactor `fw_cfg_max_cpus()` Return 0 instead of -1 in case of error. Both values indicate an error has happened. Adapt `cpu_bus_scan()` accordingly. Change-Id: I0f83fdc41c20ed3aae80829432fc84024f5b9b47 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-i440fx/northbridge.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/58918/1 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 01be2c3..3206e4c 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -133,7 +133,7 @@ unsigned short max_cpus; if (!fw_cfg_present()) - return -1; + return 0; fw_cfg_get(FW_CFG_MAX_CPUS, &max_cpus, sizeof(max_cpus)); return max_cpus; diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index d041b0c..9785a3a 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -265,11 +265,11 @@ static void cpu_bus_scan(struct device *bus) { - int max_cpus = fw_cfg_max_cpus(); + unsigned int max_cpus = fw_cfg_max_cpus(); struct device *cpu; int i; - if (max_cpus < 0) + if (max_cpus == 0) return; /* * Do not install more CPUs than supported by coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/58918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f83fdc41c20ed3aae80829432fc84024f5b9b47 Gerrit-Change-Number: 58918 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel: Use unsigned types in `get_cpu_count()`
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58917 ) Change subject: cpu/intel: Use unsigned types in `get_cpu_count()` ...................................................................... cpu/intel: Use unsigned types in `get_cpu_count()` Change-Id: Id95e45a3eba384a61c02016b7663ec71c3ae1865 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c 4 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/58917/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 2ab77b3..d4f3587 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -588,8 +588,8 @@ static int get_cpu_count(void) { msr_t msr; - int num_threads; - int num_cores; + unsigned int num_threads; + unsigned int num_cores; msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index 9a1fc42..bc53214 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -23,7 +23,7 @@ static int get_cpu_count(void) { const struct cpuid_result cpuid1 = cpuid(1); - const char cores = (cpuid1.ebx >> 16) & 0xf; + const unsigned int cores = (cpuid1.ebx >> 16) & 0xf; printk(BIOS_DEBUG, "CPU has %u cores.\n", cores); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 30519c0..e77f9aa 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -124,8 +124,8 @@ static int get_cpu_count(void) { msr_t msr; - int num_threads; - int num_cores; + unsigned int num_threads; + unsigned int num_cores; msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d240f53..9de6b38 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -380,8 +380,8 @@ static int get_cpu_count(void) { msr_t msr; - int num_threads; - int num_cores; + unsigned int num_threads; + unsigned int num_cores; msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; -- To view, visit https://review.coreboot.org/c/coreboot/+/58917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e45a3eba384a61c02016b7663ec71c3ae1865 Gerrit-Change-Number: 58917 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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