coreboot-gerrit November 2021

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Change in coreboot[master]: soc/amd/cezanne/include/aoac_defs: drop leading newline
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58863 ) Change subject: soc/amd/cezanne/include/aoac_defs: drop leading newline ...................................................................... soc/amd/cezanne/include/aoac_defs: drop leading newline Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8458fbee7edd19117a207f39ac8f9575b1374fbc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58863 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/include/soc/aoac_defs.h 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/aoac_defs.h b/src/soc/amd/cezanne/include/soc/aoac_defs.h index 5309cb0..25311dd 100644 --- a/src/soc/amd/cezanne/include/soc/aoac_defs.h +++ b/src/soc/amd/cezanne/include/soc/aoac_defs.h @@ -1,4 +1,3 @@ - /* SPDX-License-Identifier: GPL-2.0-only */ #ifndef AMD_CEZANNE_AOAC_DEFS_H 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8458fbee7edd19117a207f39ac8f9575b1374fbc Gerrit-Change-Number: 58863 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guards
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58862 ) Change subject: soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guards ...................................................................... soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guards Somehow missed renaming those when creating the coreboot support for Cezanne. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I13c28f67d32ba987987cfc2b45e248d535ccdca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58862 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/include/soc/platform_descriptors.h M src/soc/amd/cezanne/include/soc/uart.h 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/platform_descriptors.h b/src/soc/amd/cezanne/include/soc/platform_descriptors.h index 3a4bc62..d6d65f0 100644 --- a/src/soc/amd/cezanne/include/soc/platform_descriptors.h +++ b/src/soc/amd/cezanne/include/soc/platform_descriptors.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef AMD_PICASSO_PLATFORM_DESCRIPTORS_H -#define AMD_PICASSO_PLATFORM_DESCRIPTORS_H +#ifndef AMD_CEZANNE_PLATFORM_DESCRIPTORS_H +#define AMD_CEZANNE_PLATFORM_DESCRIPTORS_H #include <types.h> #include <platform_descriptors.h> @@ -14,4 +14,4 @@ void mb_pre_fspm(void); -#endif /* AMD_PICASSO_PLATFORM_DESCRIPTORS_H */ +#endif /* AMD_CEZANNE_PLATFORM_DESCRIPTORS_H */ diff --git a/src/soc/amd/cezanne/include/soc/uart.h b/src/soc/amd/cezanne/include/soc/uart.h index 9b99cd4..8affe10 100644 --- a/src/soc/amd/cezanne/include/soc/uart.h +++ b/src/soc/amd/cezanne/include/soc/uart.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef AMD_PICASSO_UART_H -#define AMD_PICASSO_UART_H +#ifndef AMD_CEZANNE_UART_H +#define AMD_CEZANNE_UART_H #include <types.h> void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ -#endif /* AMD_PICASSO_UART_H */ +#endif /* AMD_CEZANNE_UART_H */ 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13c28f67d32ba987987cfc2b45e248d535ccdca9 Gerrit-Change-Number: 58862 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/*/cpu: handle mp_init_with_smm failure
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58859 ) Change subject: soc/amd/*/cpu: handle mp_init_with_smm failure ...................................................................... soc/amd/*/cpu: handle mp_init_with_smm failure When the mp_init_with_smm call returns a failure, coreboot can't just continue with the initialization and boot process due to the system being in a bad state. Ignoring the failure here would just cause the boot process failing elsewhere where it may not be obvious that the failed multi-processor initialization step was the root cause of that. I'm not 100% sure if calling do_cold_reset or calling die_with_post_code is the better option here. Calling do_cold_reset likely here would likely result in a boot-failure loop, so I call die_with_post_code here. BUG=b:193809448 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58859 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/cpu.c M src/soc/amd/picasso/cpu.c M src/soc/amd/stoneyridge/cpu.c 3 files changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index c3d89bf..440b5ba 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -51,9 +51,9 @@ void mp_init_cpus(struct bus *cpu_bus) { - /* Clear for take-off */ - /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + die_with_post_code(POST_HW_INIT_FAILURE, + "mp_init_with_smm failed. Halting.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 9822326..b80b0f7 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -55,9 +55,9 @@ void mp_init_cpus(struct bus *cpu_bus) { - /* Clear for take-off */ - /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + die_with_post_code(POST_HW_INIT_FAILURE, + "mp_init_with_smm failed. Halting.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 0655032..6be76bf 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -52,9 +52,9 @@ void mp_init_cpus(struct bus *cpu_bus) { - /* Clear for take-off */ - /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + die_with_post_code(POST_HW_INIT_FAILURE, + "mp_init_with_smm failed. Halting.\n"); /* The flash is now no longer cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 Gerrit-Change-Number: 58859 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [RFC] ChromeOS: Add DECLARE_x_CROS_GPIOS()
by build bot (Jenkins) (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58899 ) Change subject: [RFC] ChromeOS: Add DECLARE_x_CROS_GPIOS() ...................................................................... Patch Set 4: (4 comments) File src/vendorcode/google/chromeos/chromeos.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132203): https://review.coreboot.org/c/coreboot/+/58899/comment/59ebac5e_c372d984 PS4, Line 108: #define DECLARE_CROS_GPIOS(x) \ Macros with flow control statements should be avoided Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132203): https://review.coreboot.org/c/coreboot/+/58899/comment/e3c5ebf5_0a21d10b PS4, Line 109: const struct cros_gpio *variant_cros_gpios(size_t *num) \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132203): https://review.coreboot.org/c/coreboot/+/58899/comment/bbf8e039_e1f2c3f9 PS4, Line 115: #define DECLARE_WEAK_CROS_GPIOS(x) \ Macros with flow control statements should be avoided Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132203): https://review.coreboot.org/c/coreboot/+/58899/comment/3525fae5_9a371e7a PS4, Line 116: const struct cros_gpio *__weak variant_cros_gpios(size_t *num) \ please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/58899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Gerrit-Change-Number: 58899 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:36:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/amd/mtrr: Remove topmem global variables
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58693 ) Change subject: cpu/amd/mtrr: Remove topmem global variables ...................................................................... cpu/amd/mtrr: Remove topmem global variables The comments are not correct anymore. With AGESA there is no need to synchronize TOM_MEMx msr's between AP's. It's also not the best place to do so anyway. Change-Id: Iecbe1553035680b7c3780338070b852606d74d15 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58693 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/amd/mtrr/amd_mtrr.c M src/include/cpu/amd/mtrr.h M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/northbridge.c 8 files changed, 16 insertions(+), 82 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 7502ca8..d17eedd 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -3,54 +3,11 @@ #include <amdblocks/biosram.h> #include <console/console.h> #include <device/device.h> -#include <arch/cpu.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> -#include <cpu/x86/cache.h> - -/* These will likely move to some device node or cbmem. */ -static uint64_t amd_topmem = 0; -static uint64_t amd_topmem2 = 0; - -uint64_t bsp_topmem(void) -{ - return amd_topmem; -} - -uint64_t bsp_topmem2(void) -{ - return amd_topmem2; -} - -/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers, - * so they can be distributed to AP CPUs. Not strictly MTRRs, - * but this is not that bad a place to have this code. - */ -void setup_bsp_ramtop(void) -{ - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, - "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, - "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - - amd_topmem = (uint64_t) msr.hi << 32 | msr.lo; - amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo; -} void add_uma_resource_below_tolm(struct device *nb, int idx) { - uint32_t topmem = bsp_topmem(); + uint32_t topmem = amd_topmem(); uint32_t top_of_cacheable = restore_top_of_low_cacheable(); if (top_of_cacheable == topmem) diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 9a943ac..6fe1628 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -66,10 +66,16 @@ ); } -/* To distribute topmem MSRs to APs. */ -void setup_bsp_ramtop(void); -uint64_t bsp_topmem(void); -uint64_t bsp_topmem2(void); +static inline uint64_t amd_topmem(void) +{ + return rdmsr(TOP_MEM).lo; +} + +static inline uint64_t amd_topmem2(void) +{ + msr_t msr = rdmsr(TOP_MEM2); + return (uint64_t)msr.hi << 32 | msr.lo; +} #endif #endif /* CPU_AMD_MTRR_H */ diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 4aed96b..4b4ab67 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -818,13 +818,6 @@ static void root_complex_enable_dev(struct device *dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index fe56736..bd0a5c8 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -737,7 +737,7 @@ sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + uint64_t topmem2 = amd_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } @@ -900,13 +900,6 @@ static void root_complex_enable_dev(struct device *dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 21b4d69..3d5313a 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -750,7 +750,7 @@ sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + uint64_t topmem2 = amd_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } @@ -922,13 +922,6 @@ static void root_complex_enable_dev(struct device *dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index f1c5e23..332bf1ac 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -770,7 +770,7 @@ pci_domain_read_resources(dev); /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ - mmio_basek = bsp_topmem() >> 10; + mmio_basek = amd_topmem() >> 10; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare @@ -826,7 +826,7 @@ sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + uint64_t topmem2 = amd_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } @@ -995,13 +995,6 @@ static void root_complex_enable_dev(struct device *dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 5cc52b6..666deda 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -131,7 +131,6 @@ static void soc_init(void *chip_info) { fch_init(chip_info); - setup_bsp_ramtop(); } static void soc_final(void *chip_info) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index d5231ad..5d5ed7a 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -332,7 +332,7 @@ */ void amd_initcpuio(void) { - uintptr_t topmem = bsp_topmem(); + uintptr_t topmem = amd_topmem(); uintptr_t base, limit; /* Enable legacy video routing: D18F1xF4 VGA Enable */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecbe1553035680b7c3780338070b852606d74d15 Gerrit-Change-Number: 58693 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/strago: Fix some CHROMEOS guards
by Kyösti Mälkki (Code Review) 03 Nov '21

03 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58924 ) Change subject: intel/strago: Fix some CHROMEOS guards ...................................................................... intel/strago: Fix some CHROMEOS guards Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/chromeos.c 2 files changed, 6 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/58924/1 diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index 21ae380..511a9b9 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -2,11 +2,10 @@ bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c -romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +all-y += chromeos.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-y += ec.c +ramstage-y += gpio.c ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 1a945eb..0fd63c8 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -23,14 +23,13 @@ int get_write_protect_state(void) { /* - * The vboot loader queries this function in romstage. The GPIOs have + * This function might get queried early in romstage. The GPIOs have * not been set up yet as that configuration is done in ramstage. * Configuring this GPIO as input so that there isn't any ambiguity * in the reading. */ -#if ENV_ROMSTAGE - gpio_input_pullup(WP_GPIO); -#endif + if (ENV_ROMSTAGE_OR_BEFORE) + gpio_input_pullup(WP_GPIO); /* WP is enabled when the pin is reading high. */ return !!gpio_get(WP_GPIO); -- To view, visit https://review.coreboot.org/c/coreboot/+/58924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4 Gerrit-Change-Number: 58924 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/amd/mtrr: Remove topmem global variables
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Marshall Dawson, Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58693 ) Change subject: cpu/amd/mtrr: Remove topmem global variables ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecbe1553035680b7c3780338070b852606d74d15 Gerrit-Change-Number: 58693 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:36:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/Kconfig: Remove unused CPU_ADDR_BITS
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58688 ) Change subject: cpu/x86/Kconfig: Remove unused CPU_ADDR_BITS ...................................................................... cpu/x86/Kconfig: Remove unused CPU_ADDR_BITS Change-Id: I88f62c18b814ac0ddd356944359e727d6e3bba5a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58688 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> --- M src/cpu/amd/agesa/family14/Kconfig M src/cpu/amd/agesa/family15tn/Kconfig M src/cpu/amd/agesa/family16kb/Kconfig M src/cpu/amd/pi/00730F01/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/x86/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig 12 files changed, 0 insertions(+), 64 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Mariusz Szafrański: Looks good to me, approved diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 103903f..a2790a1 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -3,11 +3,3 @@ config CPU_AMD_AGESA_FAMILY14 bool select X86_AMD_FIXED_MTRRS - -if CPU_AMD_AGESA_FAMILY14 - -config CPU_ADDR_BITS - int - default 36 - -endif diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 8c52e9a..a0288d7 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -4,11 +4,3 @@ bool select IDS_OPTIONS_HOOKED_UP select X86_AMD_FIXED_MTRRS - -if CPU_AMD_AGESA_FAMILY15_TN - -config CPU_ADDR_BITS - int - default 48 - -endif diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index e41ddec..08e8009 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -6,10 +6,6 @@ if CPU_AMD_AGESA_FAMILY16_KB -config CPU_ADDR_BITS - int - default 40 - config FORCE_AM1_SOCKET_SUPPORT bool default n diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index 5296ee6..6fd6332 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -5,11 +5,3 @@ select X86_AMD_FIXED_MTRRS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_UNDISCLOSED - -if CPU_AMD_PI_00730F01 - -config CPU_ADDR_BITS - int - default 40 - -endif diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index ac45cfa..76e0423 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -11,11 +11,3 @@ select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - -if CPU_INTEL_MODEL_106CX - -config CPU_ADDR_BITS - int - default 32 - -endif diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index fb5b541..44c9cb6 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -90,10 +90,6 @@ non-eviction mode and therefore need to be careful to avoid eviction. -config CPU_ADDR_BITS - int - default 36 - config LOGICAL_CPUS bool default y diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index c2423cd..65bf2bf 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -204,10 +204,6 @@ depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A default "apu/amdfw" -config CPU_ADDR_BITS - int - default 48 - config MMCONF_BASE_ADDRESS default 0xF8000000 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5d1c0d4..6fc4825 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -200,10 +200,6 @@ hex default 0x10000000 -config CPU_ADDR_BITS - int - default 48 - config MMCONF_BASE_ADDRESS default 0xF8000000 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 36eecb1..ec36b34 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -108,10 +108,6 @@ help Increase this value if preram cbmem console is getting truncated -config CPU_ADDR_BITS - int - default 48 - config BOTTOMIO_POSITION hex "Bottom of 32-bit IO space" default 0xD0000000 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index dca95e3..9f1cb8e 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -50,10 +50,6 @@ int default 4 -config CPU_ADDR_BITS - int - default 36 - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 3c87943..bac7bdb 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -20,10 +20,6 @@ int default 255 -config CPU_ADDR_BITS - int - default 46 - config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 528f415..444968d 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -15,10 +15,6 @@ int default 2 -config CPU_ADDR_BITS - int - default 46 - # For 2S config, the number of cpus could be as high as # 2 threads * 20 cores * 2 sockets config MAX_CPUS -- To view, visit https://review.coreboot.org/c/coreboot/+/58688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88f62c18b814ac0ddd356944359e727d6e3bba5a Gerrit-Change-Number: 58688 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58689 ) Change subject: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions ...................................................................... cpu/amd/mtrr/amd_mtrr.c: Remove unused functions AGESA sets up MTRRs so these functions are now unused. Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58689 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/mtrr/amd_mtrr.c M src/include/cpu/amd/mtrr.h 5 files changed, 9 insertions(+), 97 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 78234b6..4cf0f45 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -25,9 +25,7 @@ disable_cache(); /* * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set - * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. - * TODO: - * amd_setup_mtrrs(); + * by coreboot. */ /* Enable access to AMD RdDram and WrDram extension bits */ diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 245cdf3..d13fb9b 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -25,9 +25,10 @@ u32 siblings; #endif - //enable_cache(); - //amd_setup_mtrrs(); - //x86_mtrr_check(); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. + */ disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index c86f8ac..2915565 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -23,9 +23,10 @@ u32 siblings; #endif - //enable_cache(); - //amd_setup_mtrrs(); - //x86_mtrr_check(); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. + */ disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 8c703f5..7502ca8 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -48,25 +48,6 @@ amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo; } -static void setup_ap_ramtop(void) -{ - msr_t msr; - uint64_t v; - - v = bsp_topmem(); - if (!v) - return; - - msr.hi = v >> 32; - msr.lo = (uint32_t) v; - wrmsr(TOP_MEM, msr); - - v = bsp_topmem2(); - msr.hi = v >> 32; - msr.lo = (uint32_t) v; - wrmsr(TOP_MEM2, msr); -} - void add_uma_resource_below_tolm(struct device *nb, int idx) { uint32_t topmem = bsp_topmem(); @@ -83,71 +64,3 @@ uma_resource(nb, idx, uma_base / KiB, uma_size / KiB); } - -void amd_setup_mtrrs(void) -{ - unsigned long i; - msr_t msr, sys_cfg; - // Test if this CPU is a Fam 0Fh rev. F or later - const int cpu_id = cpuid_eax(0x80000001); - printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id); - const int has_tom2wb = - // ExtendedFamily > 0 - (((cpu_id>>20)&0xf) > 0) || - // Family == 0F - ((((cpu_id>>8)&0xf) == 0xf) && - // Rev>=F deduced from rev tables - (((cpu_id>>16)&0xf) >= 0x4)); - if (has_tom2wb) - printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n"); - - /* Enable the access to AMD RdDram and WrDram extension bits */ - disable_cache(); - sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, sys_cfg); - enable_cache(); - - /* Setup fixed MTRRs, but do not enable them just yet. */ - x86_setup_fixed_mtrrs_no_enable(); - - disable_cache(); - - setup_ap_ramtop(); - - /* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ - sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); - if (bsp_topmem2() > (uint64_t)1 << 32) { - sys_cfg.lo |= SYSCFG_MSR_TOM2En; - if (has_tom2wb) - sys_cfg.lo |= SYSCFG_MSR_TOM2WB; - } - - /* zero the IORR's before we enable to prevent - * undefined side effects. - */ - msr.lo = msr.hi = 0; - for (i = MTRR_IORR0_BASE; i <= MTRR_IORR1_MASK; i++) - wrmsr(i, msr); - - /* Enable Variable Mtrrs - * Enable the RdMem and WrMem bits in the fixed mtrrs. - * Disable access to the RdMem and WrMem in the fixed mtrr. - */ - sys_cfg.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn; - sys_cfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, sys_cfg); - - enable_fixed_mtrr(); - - enable_cache(); - - /* Now that I have mapped what is memory and what is not - * Set up the mtrrs so we can cache the memory. - */ - - // Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need - // variable MTRR to span memory above 4GB - // Lower revisions K8 need variable MTRR over 4GB - x86_setup_var_mtrrs(cpu_phys_address_size(), has_tom2wb ? 0 : 1); -} diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 608a9df..9a943ac 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -43,7 +43,6 @@ #include <cpu/x86/msr.h> #include <stdint.h> -void amd_setup_mtrrs(void); struct device; void add_uma_resource_below_tolm(struct device *nb, int idx); -- To view, visit https://review.coreboot.org/c/coreboot/+/58689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Gerrit-Change-Number: 58689 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Arthur Heymans, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58689 ) Change subject: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Gerrit-Change-Number: 58689 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:32:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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