coreboot-gerrit November 2021

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Change in coreboot[master]: cpu/x86/Kconfig: Remove unused CPU_ADDR_BITS
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58688 ) Change subject: cpu/x86/Kconfig: Remove unused CPU_ADDR_BITS ...................................................................... cpu/x86/Kconfig: Remove unused CPU_ADDR_BITS Change-Id: I88f62c18b814ac0ddd356944359e727d6e3bba5a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58688 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> --- M src/cpu/amd/agesa/family14/Kconfig M src/cpu/amd/agesa/family15tn/Kconfig M src/cpu/amd/agesa/family16kb/Kconfig M src/cpu/amd/pi/00730F01/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/x86/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig 12 files changed, 0 insertions(+), 64 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Mariusz Szafrański: Looks good to me, approved diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 103903f..a2790a1 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -3,11 +3,3 @@ config CPU_AMD_AGESA_FAMILY14 bool select X86_AMD_FIXED_MTRRS - -if CPU_AMD_AGESA_FAMILY14 - -config CPU_ADDR_BITS - int - default 36 - -endif diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 8c52e9a..a0288d7 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -4,11 +4,3 @@ bool select IDS_OPTIONS_HOOKED_UP select X86_AMD_FIXED_MTRRS - -if CPU_AMD_AGESA_FAMILY15_TN - -config CPU_ADDR_BITS - int - default 48 - -endif diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index e41ddec..08e8009 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -6,10 +6,6 @@ if CPU_AMD_AGESA_FAMILY16_KB -config CPU_ADDR_BITS - int - default 40 - config FORCE_AM1_SOCKET_SUPPORT bool default n diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index 5296ee6..6fd6332 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -5,11 +5,3 @@ select X86_AMD_FIXED_MTRRS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_UNDISCLOSED - -if CPU_AMD_PI_00730F01 - -config CPU_ADDR_BITS - int - default 40 - -endif diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index ac45cfa..76e0423 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -11,11 +11,3 @@ select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - -if CPU_INTEL_MODEL_106CX - -config CPU_ADDR_BITS - int - default 32 - -endif diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index fb5b541..44c9cb6 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -90,10 +90,6 @@ non-eviction mode and therefore need to be careful to avoid eviction. -config CPU_ADDR_BITS - int - default 36 - config LOGICAL_CPUS bool default y diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index c2423cd..65bf2bf 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -204,10 +204,6 @@ depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A default "apu/amdfw" -config CPU_ADDR_BITS - int - default 48 - config MMCONF_BASE_ADDRESS default 0xF8000000 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5d1c0d4..6fc4825 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -200,10 +200,6 @@ hex default 0x10000000 -config CPU_ADDR_BITS - int - default 48 - config MMCONF_BASE_ADDRESS default 0xF8000000 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 36eecb1..ec36b34 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -108,10 +108,6 @@ help Increase this value if preram cbmem console is getting truncated -config CPU_ADDR_BITS - int - default 48 - config BOTTOMIO_POSITION hex "Bottom of 32-bit IO space" default 0xD0000000 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index dca95e3..9f1cb8e 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -50,10 +50,6 @@ int default 4 -config CPU_ADDR_BITS - int - default 36 - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 3c87943..bac7bdb 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -20,10 +20,6 @@ int default 255 -config CPU_ADDR_BITS - int - default 46 - config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 528f415..444968d 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -15,10 +15,6 @@ int default 2 -config CPU_ADDR_BITS - int - default 46 - # For 2S config, the number of cpus could be as high as # 2 threads * 20 cores * 2 sockets config MAX_CPUS -- To view, visit https://review.coreboot.org/c/coreboot/+/58688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88f62c18b814ac0ddd356944359e727d6e3bba5a Gerrit-Change-Number: 58688 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58689 ) Change subject: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions ...................................................................... cpu/amd/mtrr/amd_mtrr.c: Remove unused functions AGESA sets up MTRRs so these functions are now unused. Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58689 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/mtrr/amd_mtrr.c M src/include/cpu/amd/mtrr.h 5 files changed, 9 insertions(+), 97 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 78234b6..4cf0f45 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -25,9 +25,7 @@ disable_cache(); /* * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set - * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. - * TODO: - * amd_setup_mtrrs(); + * by coreboot. */ /* Enable access to AMD RdDram and WrDram extension bits */ diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 245cdf3..d13fb9b 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -25,9 +25,10 @@ u32 siblings; #endif - //enable_cache(); - //amd_setup_mtrrs(); - //x86_mtrr_check(); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. + */ disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index c86f8ac..2915565 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -23,9 +23,10 @@ u32 siblings; #endif - //enable_cache(); - //amd_setup_mtrrs(); - //x86_mtrr_check(); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. + */ disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 8c703f5..7502ca8 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -48,25 +48,6 @@ amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo; } -static void setup_ap_ramtop(void) -{ - msr_t msr; - uint64_t v; - - v = bsp_topmem(); - if (!v) - return; - - msr.hi = v >> 32; - msr.lo = (uint32_t) v; - wrmsr(TOP_MEM, msr); - - v = bsp_topmem2(); - msr.hi = v >> 32; - msr.lo = (uint32_t) v; - wrmsr(TOP_MEM2, msr); -} - void add_uma_resource_below_tolm(struct device *nb, int idx) { uint32_t topmem = bsp_topmem(); @@ -83,71 +64,3 @@ uma_resource(nb, idx, uma_base / KiB, uma_size / KiB); } - -void amd_setup_mtrrs(void) -{ - unsigned long i; - msr_t msr, sys_cfg; - // Test if this CPU is a Fam 0Fh rev. F or later - const int cpu_id = cpuid_eax(0x80000001); - printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id); - const int has_tom2wb = - // ExtendedFamily > 0 - (((cpu_id>>20)&0xf) > 0) || - // Family == 0F - ((((cpu_id>>8)&0xf) == 0xf) && - // Rev>=F deduced from rev tables - (((cpu_id>>16)&0xf) >= 0x4)); - if (has_tom2wb) - printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n"); - - /* Enable the access to AMD RdDram and WrDram extension bits */ - disable_cache(); - sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, sys_cfg); - enable_cache(); - - /* Setup fixed MTRRs, but do not enable them just yet. */ - x86_setup_fixed_mtrrs_no_enable(); - - disable_cache(); - - setup_ap_ramtop(); - - /* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ - sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); - if (bsp_topmem2() > (uint64_t)1 << 32) { - sys_cfg.lo |= SYSCFG_MSR_TOM2En; - if (has_tom2wb) - sys_cfg.lo |= SYSCFG_MSR_TOM2WB; - } - - /* zero the IORR's before we enable to prevent - * undefined side effects. - */ - msr.lo = msr.hi = 0; - for (i = MTRR_IORR0_BASE; i <= MTRR_IORR1_MASK; i++) - wrmsr(i, msr); - - /* Enable Variable Mtrrs - * Enable the RdMem and WrMem bits in the fixed mtrrs. - * Disable access to the RdMem and WrMem in the fixed mtrr. - */ - sys_cfg.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn; - sys_cfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, sys_cfg); - - enable_fixed_mtrr(); - - enable_cache(); - - /* Now that I have mapped what is memory and what is not - * Set up the mtrrs so we can cache the memory. - */ - - // Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need - // variable MTRR to span memory above 4GB - // Lower revisions K8 need variable MTRR over 4GB - x86_setup_var_mtrrs(cpu_phys_address_size(), has_tom2wb ? 0 : 1); -} diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 608a9df..9a943ac 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -43,7 +43,6 @@ #include <cpu/x86/msr.h> #include <stdint.h> -void amd_setup_mtrrs(void); struct device; void add_uma_resource_below_tolm(struct device *nb, int idx); -- To view, visit https://review.coreboot.org/c/coreboot/+/58689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Gerrit-Change-Number: 58689 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Arthur Heymans, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58689 ) Change subject: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Gerrit-Change-Number: 58689 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:32:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/amd/common/fsp: check FSP binary version.
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Name of user not set #1003801, Andrey Petrov, Patrick Rudolph, Julian Schroeder. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58869 ) Change subject: src/soc/amd/common/fsp: check FSP binary version. ...................................................................... Patch Set 1: (4 comments) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/58869/comment/72b762b1_70f5829a PS1, Line 13: //jsd ? https://review.coreboot.org/c/coreboot/+/58869/comment/8e7a7d8b_54deb8fd PS1, Line 34: #define FSP_INFO_HEADER_OFF 0x94 this is a redefinition of FSP_HDR_OFFSET https://review.coreboot.org/c/coreboot/+/58869/comment/15ba850e_833381b1 PS1, Line 35: fsp_info_header this looks like a redefinition of fsp_header right above File src/drivers/intel/fsp2_0/util.c: https://review.coreboot.org/c/coreboot/+/58869/comment/43f6067d_35f23825 PS1, Line 80: struct fsp_info_header *info = (struct fsp_info_header *) (fsp_file + FSP_INFO_HEADER_OFF); not sure why this is needed. last time i checked, soc_validate_fspm_header did what i was expecting -- To view, visit https://review.coreboot.org/c/coreboot/+/58869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf50f16b5e9793d946a95970fcdabc4c07289646 Gerrit-Change-Number: 58869 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Name of user not set #1003801 Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:30:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58689 ) Change subject: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: did a manual rebase, since this patch didn't apply any more after CB:58579 -- To view, visit https://review.coreboot.org/c/coreboot/+/58689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Gerrit-Change-Number: 58689 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:24:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Arthur Heymans. Felix Held has uploaded a new patch set (#3) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/58689 ) Change subject: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions ...................................................................... cpu/amd/mtrr/amd_mtrr.c: Remove unused functions AGESA sets up MTRRs so these functions are now unused. Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/mtrr/amd_mtrr.c M src/include/cpu/amd/mtrr.h 5 files changed, 9 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/58689/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Gerrit-Change-Number: 58689 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/variants/lillipup: add generic SPDs
by Nick Vaccaro (Code Review) 03 Nov '21

03 Nov '21

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46349 ) Change subject: mb/google/volteer/variants/lillipup: add generic SPDs ...................................................................... mb/google/volteer/variants/lillipup: add generic SPDs Add generic LPDDR4x SPD support for the following three memory parts: K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E512M32D2NP-046 WT:F BUG=b:170264065 TEST=none Change-Id: Ie3163763a0ce291f27c43181d35c070c218b461d Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- A src/mainboard/google/volteer/variants/lillipup/memory/Makefile.inc A src/mainboard/google/volteer/variants/lillipup/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lillipup/memory/mem_list_variant.txt 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46349/1 diff --git a/src/mainboard/google/volteer/variants/lillipup/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lillipup/memory/Makefile.inc new file mode 100644 index 0000000..b7e6944 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lillipup/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:F diff --git a/src/mainboard/google/volteer/variants/lillipup/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lillipup/memory/dram_id.generated.txt new file mode 100644 index 0000000..dc87e04 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lillipup/memory/dram_id.generated.txt @@ -0,0 +1,4 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E512M32D2NP-046 WT:F 0 (0000) diff --git a/src/mainboard/google/volteer/variants/lillipup/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lillipup/memory/mem_list_variant.txt new file mode 100644 index 0000000..d0273dc --- /dev/null +++ b/src/mainboard/google/volteer/variants/lillipup/memory/mem_list_variant.txt @@ -0,0 +1,3 @@ +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E512M32D2NP-046 WT:F -- To view, visit https://review.coreboot.org/c/coreboot/+/46349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3163763a0ce291f27c43181d35c070c218b461d Gerrit-Change-Number: 46349 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Michael Niewöhner (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 46: Code-Review-2 (1 comment) Patchset: PS46: > So this can wait until there is an Intel customer who needs it, right? And when […] Wow. So this is another example for Intel making use of a open-source project, while not contributing to it, not providing at least a minimal open-source example and still handing off support to the open-source communities? [1] What the ... Well then, as long as Intel is not willing to upstream minimal sample code to Zephyr and/or coreboot, this gets a -2 from me. @Lean Thank you for trying to convince them! @Nico I wonder how you want to integrate that minimal sample exactly. That minimal sample code should be in the Zephyr project IMO, so we might add it to 3rdparty/Zephyr and build it like other external stuff (payloads, libgfxinit). Is that what you have in mind? [1] see table saying "Implementation = Intel, Support = Zephyr RTOS and Open Source Community" https://www.intel.de/content/www/de/de/products/docs/processors/embedded/en… -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 46 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:01:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel: Use unsigned types in `get_cpu_count()`
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58917 ) Change subject: cpu/intel: Use unsigned types in `get_cpu_count()` ...................................................................... Patch Set 1: (1 comment) File src/cpu/intel/model_1067x/mp_init.c: https://review.coreboot.org/c/coreboot/+/58917/comment/2f855e54_e26afb15 PS1, Line 26: 0xf > unrelated to what this patch does and not that it would matter here, but isn't that field 8 bits? I haven't checked, but it doesn't matter (these CPUs have at most 4 cores) -- To view, visit https://review.coreboot.org/c/coreboot/+/58917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e45a3eba384a61c02016b7663ec71c3ae1865 Gerrit-Change-Number: 58917 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Nov 2021 17:41:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] ChromeOS: Move cros_get_gpio_value()
by Kyösti Mälkki (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58898 to look at the new patch set (#4). Change subject: [WIP] ChromeOS: Move cros_get_gpio_value() ...................................................................... [WIP] ChromeOS: Move cros_get_gpio_value() Change-Id: Id2a8427e8cd34abde98a267bd086eb4143433d0b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/sarien/chromeos.c M src/vendorcode/google/chromeos/acpi.c M src/vendorcode/google/chromeos/chromeos.h 5 files changed, 24 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/58898/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2a8427e8cd34abde98a267bd086eb4143433d0b Gerrit-Change-Number: 58898 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021