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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58869 )
Change subject: src/soc/amd/common/fsp: check FSP binary version.
......................................................................
Patch Set 1:
(4 comments)
File src/drivers/intel/fsp2_0/include/fsp/info_header.h:
https://review.coreboot.org/c/coreboot/+/58869/comment/72b762b1_70f5829a
PS1, Line 13: //jsd
?
https://review.coreboot.org/c/coreboot/+/58869/comment/8e7a7d8b_54deb8fd
PS1, Line 34: #define FSP_INFO_HEADER_OFF 0x94
this is a redefinition of FSP_HDR_OFFSET
https://review.coreboot.org/c/coreboot/+/58869/comment/15ba850e_833381b1
PS1, Line 35: fsp_info_header
this looks like a redefinition of fsp_header right above
File src/drivers/intel/fsp2_0/util.c:
https://review.coreboot.org/c/coreboot/+/58869/comment/43f6067d_35f23825
PS1, Line 80: struct fsp_info_header *info = (struct fsp_info_header *) (fsp_file + FSP_INFO_HEADER_OFF);
not sure why this is needed. last time i checked, soc_validate_fspm_header did what i was expecting
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Change subject: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
did a manual rebase, since this patch didn't apply any more after CB:58579
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Felix Held has uploaded a new patch set (#3) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/58689 )
Change subject: cpu/amd/mtrr/amd_mtrr.c: Remove unused functions
......................................................................
cpu/amd/mtrr/amd_mtrr.c: Remove unused functions
AGESA sets up MTRRs so these functions are now unused.
Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/amd/agesa/family14/model_14_init.c
M src/cpu/amd/agesa/family15tn/model_15_init.c
M src/cpu/amd/agesa/family16kb/model_16_init.c
M src/cpu/amd/mtrr/amd_mtrr.c
M src/include/cpu/amd/mtrr.h
5 files changed, 9 insertions(+), 97 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/58689/3
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )
Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
Patch Set 46: Code-Review-2
(1 comment)
Patchset:
PS46:
> So this can wait until there is an Intel customer who needs it, right? And when […]
Wow. So this is another example for Intel making use of a open-source project, while not contributing to it, not providing at least a minimal open-source example and still handing off support to the open-source communities? [1] What the ...
Well then, as long as Intel is not willing to upstream minimal sample code to Zephyr and/or coreboot, this gets a -2 from me.
@Lean Thank you for trying to convince them!
@Nico I wonder how you want to integrate that minimal sample exactly. That minimal sample code should be in the Zephyr project IMO, so we might add it to 3rdparty/Zephyr and build it like other external stuff (payloads, libgfxinit). Is that what you have in mind?
[1] see table saying "Implementation = Intel, Support = Zephyr RTOS and Open Source Community" https://www.intel.de/content/www/de/de/products/docs/processors/embedded/en…
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Change subject: cpu/intel: Use unsigned types in `get_cpu_count()`
......................................................................
Patch Set 1:
(1 comment)
File src/cpu/intel/model_1067x/mp_init.c:
https://review.coreboot.org/c/coreboot/+/58917/comment/2f855e54_e26afb15
PS1, Line 26: 0xf
> unrelated to what this patch does and not that it would matter here, but isn't that field 8 bits?
I haven't checked, but it doesn't matter (these CPUs have at most 4 cores)
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google,intel: Fix indirect includes
......................................................................
mb/google,intel: Fix indirect includes
We have <baseboard/variants.h> that currently pulls
in <vc/google/chromeos/chromeos.h>, addressing that
triggered some errors.
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/amd/majolica/chromeos.c
M src/mainboard/emulation/qemu-q35/chromeos.c
M src/mainboard/google/auron/chromeos.c
M src/mainboard/google/brya/chromeos.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/dedede/chromeos.c
M src/mainboard/google/deltaur/chromeos.c
M src/mainboard/google/deltaur/variants/deltan/memory.c
M src/mainboard/google/drallion/chromeos.c
M src/mainboard/google/eve/chromeos.c
M src/mainboard/google/fizz/chromeos.c
M src/mainboard/google/fizz/mainboard.c
M src/mainboard/google/glados/chromeos.c
M src/mainboard/google/guybrush/chromeos.c
M src/mainboard/google/hatch/chromeos.c
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
M src/mainboard/google/jecht/chromeos.c
M src/mainboard/google/kahlee/chromeos.c
M src/mainboard/google/octopus/chromeos.c
M src/mainboard/google/poppy/chromeos.c
M src/mainboard/google/reef/chromeos.c
M src/mainboard/google/sarien/chromeos.c
M src/mainboard/google/volteer/chromeos.c
M src/mainboard/google/zork/chromeos.c
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/adlrvp/memory.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/intel/coffeelake_rvp/chromeos.c
M src/mainboard/intel/glkrvp/chromeos.c
M src/mainboard/intel/icelake_rvp/chromeos.c
M src/mainboard/intel/jasperlake_rvp/chromeos.c
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kunimitsu/chromeos.c
M src/mainboard/intel/shadowmountain/chromeos.c
M src/mainboard/intel/strago/chromeos.c
M src/mainboard/intel/tglrvp/chromeos.c
36 files changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/58921/2
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: [RFC] ChromeOS: Promote variant_cros_gpio()
......................................................................
[RFC] ChromeOS: Promote variant_cros_gpio()
The only purpose of mainboard_chromeos_acpi_generate()
was to pass cros_gpio array for ACPI \\OIPG package
generation.
Promote variant_cros_gpio() from baseboards to ChromeOS
declaration.
Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/amd/majolica/chromeos.c
M src/mainboard/emulation/qemu-q35/chromeos.c
M src/mainboard/google/auron/chromeos.c
M src/mainboard/google/beltino/chromeos.c
M src/mainboard/google/brya/chromeos.c
M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/butterfly/chromeos.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/dedede/chromeos.c
M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/deltaur/chromeos.c
M src/mainboard/google/deltaur/variants/baseboard/gpio.c
M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h
M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/drallion/chromeos.c
M src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
M src/mainboard/google/eve/chromeos.c
M src/mainboard/google/fizz/chromeos.c
M src/mainboard/google/fizz/variants/baseboard/gpio.c
M src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/glados/chromeos.c
M src/mainboard/google/guybrush/chromeos.c
M src/mainboard/google/hatch/chromeos.c
M src/mainboard/google/hatch/variants/baseboard/gpio.c
M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/jecht/chromeos.c
M src/mainboard/google/kahlee/chromeos.c
M src/mainboard/google/link/chromeos.c
M src/mainboard/google/octopus/chromeos.c
M src/mainboard/google/octopus/variants/baseboard/gpio.c
M src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/parrot/chromeos.c
M src/mainboard/google/poppy/chromeos.c
M src/mainboard/google/poppy/variants/baseboard/gpio.c
M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/rambi/chromeos.c
M src/mainboard/google/reef/chromeos.c
M src/mainboard/google/reef/variants/baseboard/gpio.c
M src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/reef/variants/coral/gpio.c
M src/mainboard/google/sarien/chromeos.c
M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h
M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h
M src/mainboard/google/slippy/chromeos.c
M src/mainboard/google/stout/chromeos.c
M src/mainboard/google/volteer/chromeos.c
M src/mainboard/google/volteer/variants/baseboard/gpio.c
M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/zork/chromeos.c
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/adlrvp/gpio.c
M src/mainboard/intel/adlrvp/gpio_m.c
M src/mainboard/intel/adlrvp/include/baseboard/variants.h
M src/mainboard/intel/baskingridge/chromeos.c
M src/mainboard/intel/coffeelake_rvp/chromeos.c
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h
M src/mainboard/intel/emeraldlake2/chromeos.c
M src/mainboard/intel/glkrvp/chromeos.c
M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h
M src/mainboard/intel/icelake_rvp/chromeos.c
M src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h
M src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c
M src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c
M src/mainboard/intel/jasperlake_rvp/chromeos.c
M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kunimitsu/chromeos.c
M src/mainboard/intel/shadowmountain/chromeos.c
M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
M src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h
M src/mainboard/intel/strago/chromeos.c
M src/mainboard/intel/tglrvp/chromeos.c
M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
M src/mainboard/intel/wtm2/chromeos.c
M src/mainboard/samsung/lumpy/chromeos.c
M src/mainboard/samsung/stumpy/chromeos.c
M src/vendorcode/google/chromeos/acpi.c
M src/vendorcode/google/chromeos/chromeos.h
M src/vendorcode/google/chromeos/gnvs.c
84 files changed, 105 insertions(+), 313 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/58897/5
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58898
to look at the new patch set (#4).
Change subject: [WIP] ChromeOS: Move cros_get_gpio_value()
......................................................................
[WIP] ChromeOS: Move cros_get_gpio_value()
Change-Id: Id2a8427e8cd34abde98a267bd086eb4143433d0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/google/deltaur/chromeos.c
M src/mainboard/google/drallion/chromeos.c
M src/mainboard/google/sarien/chromeos.c
M src/vendorcode/google/chromeos/acpi.c
M src/vendorcode/google/chromeos/chromeos.h
5 files changed, 24 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/58898/4
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58916 )
Change subject: soc/intel/baytrail: Make `num_cpus` unsigned
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Patch Set 1: Code-Review+2
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