coreboot-gerrit November 2021

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Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO drivers
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58836 ) Change subject: soc/mediatek/mt8186: Add GPIO drivers ...................................................................... soc/mediatek/mt8186: Add GPIO drivers Add GPIO drivers to let other module control GPIOs. TEST=build pass BUG=b:202871018 Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com> Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/58836 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/gpio.c A src/soc/mediatek/mt8186/include/soc/gpio.h A src/soc/mediatek/mt8186/include/soc/gpio_base.h 4 files changed, 751 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 72d67cc..76dac4b 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -1,12 +1,14 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8186),y) bootblock-y += bootblock.c +bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c wdt.c +verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += spi.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c @@ -14,12 +16,14 @@ romstage-y += ../common/cbmem.c romstage-y += emi.c +romstage-y += ../common/gpio.c gpio.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c wdt.c ramstage-y += emi.c +ramstage-y += ../common/gpio.c gpio.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8186/gpio.c b/src/soc/mediatek/mt8186/gpio.c new file mode 100644 index 0000000..bd3ab65 --- /dev/null +++ b/src/soc/mediatek/mt8186/gpio.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.1 + */ + +#include <device/mmio.h> +#include <gpio.h> + +static void *gpio_find_reg_addr(gpio_t gpio) +{ + void *reg_addr; + switch (gpio.base & 0x0f) { + case 1: + reg_addr = (void *)IOCFG_LT_BASE; + break; + case 2: + reg_addr = (void *)IOCFG_LM_BASE; + break; + case 3: + reg_addr = (void *)IOCFG_LB_BASE; + break; + case 4: + reg_addr = (void *)IOCFG_BL_BASE; + break; + case 5: + reg_addr = (void *)IOCFG_RB_BASE; + break; + case 6: + reg_addr = (void *)IOCFG_RT_BASE; + break; + default: + reg_addr = NULL; + break; + } + + return reg_addr; +} + +static void gpio_set_spec_pull_pupd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg1; + void *reg2; + int bit = gpio.bit; + + reg1 = gpio_find_reg_addr(gpio) + gpio.offset; + reg2 = reg1 + (gpio.base & 0xf0); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) + setbits32(reg1, BIT(bit)); + else + clrbits32(reg1, BIT(bit)); + } + + if (enable == GPIO_PULL_ENABLE) { + setbits32(reg2, 1 << bit); + } else { + clrbits32(reg2, 1 << bit); + clrbits32(reg2 + 0x010, BIT(bit)); + } +} + +static void gpio_set_pull_pu_pd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg1; + void *reg2; + int bit = gpio.bit; + + reg1 = gpio_find_reg_addr(gpio) + gpio.offset; + reg2 = reg1 - (gpio.base & 0xf0); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) { + clrbits32(reg1, BIT(bit)); + setbits32(reg2, BIT(bit)); + } else { + clrbits32(reg2, BIT(bit)); + setbits32(reg1, BIT(bit)); + } + } else { + clrbits32(reg1, BIT(bit)); + clrbits32(reg2, BIT(bit)); + } +} + +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + if (gpio.flag) + gpio_set_spec_pull_pupd(gpio, enable, select); + else + gpio_set_pull_pu_pd(gpio, enable, select); +} diff --git a/src/soc/mediatek/mt8186/include/soc/gpio.h b/src/soc/mediatek/mt8186/include/soc/gpio.h new file mode 100644 index 0000000..a47d27c --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/gpio.h @@ -0,0 +1,626 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.1 + */ + +#ifndef SOC_MEDIATEK_MT8186_GPIO_H +#define SOC_MEDIATEK_MT8186_GPIO_H + +#include <soc/addressmap.h> +#include <soc/gpio_common.h> +#include <types.h> + +enum { + MAX_GPIO_REG_BITS = 32, + MAX_GPIO_MODE_PER_REG = 8, + GPIO_MODE_BITS = 4, +}; + +#define PIN(id, name, flag, bit, base, offset, \ + func1, func2, func3, func4, func5, func6, func7) \ + PAD_##name##_ID = id, \ + PAD_##name##_FLAG = flag, \ + PAD_##name##_BIT = bit, \ + PAD_##name##_BASE = base, \ + PAD_##name##_OFFSET = offset, \ + PAD_##name##_FUNC_##func1 = 1, \ + PAD_##name##_FUNC_##func2 = 2, \ + PAD_##name##_FUNC_##func3 = 3, \ + PAD_##name##_FUNC_##func4 = 4, \ + PAD_##name##_FUNC_##func5 = 5, \ + PAD_##name##_FUNC_##func6 = 6, \ + PAD_##name##_FUNC_##func7 = 7 + +#define GPIO(name) ((gpio_t){ \ + .id = PAD_##name##_ID, \ + .flag = PAD_##name##_FLAG, \ + .bit = PAD_##name##_BIT, \ + .base = PAD_##name##_BASE, \ + .offset = PAD_##name##_OFFSET \ + }) + +enum { + PIN(0, EINT0, 0, 13, 0x16, 0x50, + I2S0_MCK, SPI0_CLK_B, I2S2_MCK, CMFLASH0, + SCP_SPI0_CK, TP_GPIO0_AO, dbg_mon_a0), + PIN(1, EINT1, 0, 14, 0x16, 0x50, + I2S0_BCK, SPI0_CSB_B, I2S2_BCK, CMFLASH1, + SCP_SPI0_CS, TP_GPIO1_AO, RES7), + PIN(2, EINT2, 0, 17, 0x16, 0x50, + I2S0_LRCK, SPI0_MO_B, I2S2_LRCK, CMFLASH2, + SCP_SPI0_MO, TP_GPIO2_AO, RES7), + PIN(3, EINT3, 0, 18, 0x16, 0x50, + I2S0_DI, SPI0_MI_B, I2S2_DI, SRCLKENAI1, + SCP_SPI0_MI, TP_GPIO3_AO, RES7), + PIN(4, EINT4, 0, 19, 0x16, 0x50, + I2S3_DO, RES2, I2S1_DO, RES4, + RES5, TP_GPIO4_AO, RES7), + PIN(5, EINT5, 0, 20, 0x16, 0x50, + EXT_FRAME_SYNC, RES2, RES3, RES4, + RES5, TP_GPIO5_AO, RES7), + PIN(6, EINT6, 0, 19, 0x24, 0x60, + I2S3_MCK, SPI1_CLK_B, I2S1_MCK, DPI_DATA22, + RES5, TP_GPIO6_AO, RES7), + PIN(7, EINT7, 0, 20, 0x24, 0x60, + I2S3_BCK, SPI1_CSB_B, I2S1_BCK, DPI_DATA23, + RES5, TP_GPIO7_AO, RES7), + PIN(8, EINT8, 0, 21, 0x24, 0x60, + I2S3_LRCK, SPI1_MO_B, I2S1_LRCK, CONN_UART0_RXD, + SSPM_URXD_AO, ADSP_UART_RX, CONN_MCU_DBGACK_N), + PIN(9, EINT9, 0, 22, 0x24, 0x60, + I2S3_DO, SPI1_MI_B, I2S1_DO, CONN_UART0_TXD, + SSPM_UTXD_AO, ADSP_UART_TX, CONN_MCU_DBGI_N), + PIN(10, EINT10, 0, 16, 0x24, 0x60, + I2S0_MCK, SPI4_CLK_A, I2S2_MCK, SPM_JTAG_TDI, + SCP_JTAG_TDI, ADSP_JTAG_TDI, CONN_MCU_TDI), + PIN(11, EINT11, 0, 17, 0x24, 0x60, + I2S0_BCK, SPI4_CSB_A, I2S2_BCK, SPM_JTAG_TRSTN, + SCP_JTAG_TRSTN, ADSP_JTAG_TRSTN, CONN_MCU_TRST_B), + PIN(12, EINT12, 0, 18, 0x24, 0x60, + I2S0_LRCK, SPI4_MO_A, I2S2_LRCK, SPM_JTAG_TCK, + SCP_JTAG_TCK, ADSP_JTAG_TCK, CONN_MCU_TCK), + PIN(13, EINT13, 0, 0, 0x23, 0x80, + I2S0_DI, SPI4_MI_A, I2S2_DI, SPM_JTAG_TDO, + SCP_JTAG_TDO, ADSP_JTAG_TDO, CONN_MCU_TDO), + PIN(14, EINT14, 0, 1, 0x23, 0x80, + RES1, RES2, CLKM0, SPM_JTAG_TMS, + SCP_JTAG_TMS, ADSP_JTAG_TMS, CONN_MCU_TMS), + PIN(15, EINT15, 0, 15, 0x16, 0x50, + EXT_FRAME_SYNC, SRCLKENAI1, CLKM1, PWM0, + RES5, RES6, RES7), + PIN(16, EINT16, 0, 16, 0x16, 0x50, + CONN_WIFI_TXD, SRCLKENAI0, CLKM2, PWM1, + RES5, RES6, RES7), + PIN(17, EINT17, 0, 9, 0x25, 0x90, + RES1, RES2, CLKM3, PWM2, + RES5, RES6, dbg_mon_a32), + PIN(18, EINT18, 0, 10, 0x25, 0x90, + RES1, CMVREF0, RES3, RES4, + RES5, SPI2_CLK_B, dbg_mon_a26), + PIN(19, CAM_PDN0, 0, 3, 0x25, 0x90, + RES1, CMVREF1, RES3, RES4, + ANT_SEL3, SPI2_CSB_B, dbg_mon_a2), + PIN(20, CAM_RST0, 0, 6, 0x25, 0x90, + RES1, CMVREF2, RES3, RES4, + ANT_SEL4, SPI2_MO_B, dbg_mon_a3), + PIN(21, CAM_PDN1, 0, 4, 0x25, 0x90, + I2S0_MCK, I2S1_MCK, I2S3_MCK, RES4, + ANT_SEL5, SPI2_MI_B, dbg_mon_a4), + PIN(22, CAM_RST1, 0, 7, 0x25, 0x90, + I2S0_BCK, I2S1_BCK, I2S3_BCK, TDM_RX_LRCK, + ANT_SEL6, RES6, dbg_mon_a5), + PIN(23, CAM_PDN2, 0, 5, 0x25, 0x90, + I2S0_LRCK, I2S1_LRCK, I2S3_LRCK, TDM_RX_BCK, + ANT_SEL7, RES6, dbg_mon_a6), + PIN(24, CAM_RST2, 0, 8, 0x25, 0x90, + I2S0_DI, I2S1_DO, I2S3_DO, TDM_RX_MCK, + RES5, RES6, dbg_mon_a7), + PIN(25, I2S2_MCK, 0, 18, 0x25, 0x90, + I2S2_MCK, PCM_CLK, SPI4_CLK_B, TDM_RX_DATA0, + RES5, RES6, dbg_mon_a8), + PIN(26, I2S2_BCK, 0, 15, 0x25, 0x90, + I2S2_BCK, PCM_SYNC, SPI4_CSB_B, TDM_RX_DATA1, + RES5, RES6, dbg_mon_a9), + PIN(27, I2S2_LRCK, 0, 17, 0x25, 0x90, + I2S2_LRCK, PCM_DI, SPI4_MO_B, TDM_RX_DATA2, + RES5, RES6, dbg_mon_a10), + PIN(28, I2S2_DI, 0, 16, 0x25, 0x90, + I2S2_DI, PCM_DO, SPI4_MI_B, TDM_RX_DATA3, + RES5, RES6, RES7), + PIN(29, ANT_SEL0, 0, 0, 0x16, 0x50, + ANT_SEL0, GPS_L1_ELNA_EN, RES3, RES4, + RES5, RES6, RES7), + PIN(30, ANT_SEL1, 0, 1, 0x16, 0x50, + ANT_SEL1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(31, ANT_SEL2, 0, 2, 0x16, 0x50, + ANT_SEL2, EXT_FRAME_SYNC, SRCLKENAI1, RES4, + RES5, RES6, RES7), + PIN(32, URXD0, 0, 25, 0x12, 0x60, + URXD0, UTXD0, ADSP_UART_RX, TP_URXD1_AO, + RES5, RES6, RES7), + PIN(33, UTXD0, 0, 27, 0x12, 0x60, + UTXD0, URXD0, ADSP_UART_TX, TP_UTXD1_AO, + RES5, RES6, RES7), + PIN(34, URXD1, 0, 26, 0x12, 0x60, + URXD1, TP_URXD2_AO, SSPM_URXD_AO, ADSP_UART_RX, + CONN_UART0_RXD, RES6, RES7), + PIN(35, UTXD1, 0, 28, 0x12, 0x60, + UTXD1, TP_UTXD2_AO, SSPM_UTXD_AO, ADSP_UART_TX, + CONN_UART0_TXD, CONN_WIFI_TXD, RES7), + PIN(36, SPI0_CLK, 0, 9, 0x12, 0x60, + SPI0_CLK_A, CLKM0, RES3, SCP_SPI0_CK, + SPINOR_CK, RES6, dbg_mon_a11), + PIN(37, SPI0_CSB, 0, 10, 0x12, 0x60, + SPI0_CSB_A, CLKM1, PWM0, SCP_SPI0_CS, + SPINOR_CS, RES6, dbg_mon_a12), + PIN(38, SPI0_MO, 0, 12, 0x12, 0x60, + SPI0_MO_A, CLKM2, PWM1, SCP_SPI0_MO, + SPINOR_IO0, RES6, dbg_mon_a13), + PIN(39, SPI0_MI, 0, 11, 0x12, 0x60, + SPI0_MI_A, CLKM3, PWM2, SCP_SPI0_MI, + SPINOR_IO1, RES6, dbg_mon_a14), + PIN(40, SPI1_CLK, 0, 13, 0x12, 0x60, + SPI1_CLK_A, SCP_SPI1_CK, RES3, UCTS0, + SPINOR_IO2, TP_UCTS1_AO, dbg_mon_a15), + PIN(41, SPI1_CSB, 0, 14, 0x12, 0x60, + SPI1_CSB_A, SCP_SPI1_CS, PWM0, URTS0, + SPINOR_IO3, TP_URTS1_AO, dbg_mon_a16), + PIN(42, SPI1_MO, 0, 16, 0x12, 0x60, + SPI1_MO_A, SCP_SPI1_MO, PWM1, UCTS1, + RES5, TP_UCTS2_AO, dbg_mon_a17), + PIN(43, SPI1_MI, 0, 15, 0x12, 0x60, + SPI1_MI_A, SCP_SPI1_MI, PWM2, URTS1, + RES5, TP_URTS2_AO, dbg_mon_a18), + PIN(44, SPI2_CK, 0, 28, 0x25, 0x90, + SPI2_CLK_A, SCP_SPI0_CK, RES3, RES4, + RES5, RES6, dbg_mon_a19), + PIN(45, SPI2_CSB, 0, 29, 0x25, 0x90, + SPI2_CSB_A, SCP_SPI0_CS, RES3, RES4, + RES5, RES6, dbg_mon_a20), + PIN(46, SPI2_MO, 0, 31, 0x25, 0x90, + SPI2_MO_A, SCP_SPI0_MO, RES3, RES4, + RES5, RES6, dbg_mon_a21), + PIN(47, SPI2_MI, 0, 30, 0x25, 0x90, + SPI2_MI_A, SCP_SPI0_MI, RES3, RES4, + RES5, RES6, dbg_mon_a22), + PIN(48, SPI3_CLK, 0, 17, 0x12, 0x60, + SPI3_CLK, TP_URXD1_AO, TP_URXD2_AO, URXD1, + I2S2_MCK, SCP_SPI0_CK, RES7), + PIN(49, SPI3_CSB, 0, 18, 0x12, 0x60, + SPI3_CSB, TP_UTXD1_AO, TP_UTXD2_AO, UTXD1, + I2S2_BCK, SCP_SPI0_CS, RES7), + PIN(50, SPI3_MO, 0, 20, 0x12, 0x60, + SPI3_MO, RES2, RES3, RES4, + I2S2_LRCK, SCP_SPI0_MO, RES7), + PIN(51, SPI3_MI, 0, 19, 0x12, 0x60, + SPI3_MI, RES2, RES3, RES4, + I2S2_DI, SCP_SPI0_MI, RES7), + PIN(52, SPI5_CLK, 0, 12, 0x23, 0x80, + SPI5_CLK, I2S2_MCK, I2S1_MCK, SCP_SPI1_CK, + LVTS_26M, DFD_TCK_XI, dbg_mon_b30), + PIN(53, SPI5_CSB, 0, 13, 0x23, 0x80, + SPI5_CSB, I2S2_BCK, I2S1_BCK, SCP_SPI1_CS, + LVTS_FOUT, DFD_TDI, dbg_mon_b31), + PIN(54, SPI5_MO, 0, 15, 0x23, 0x80, + SPI5_MO, I2S2_LRCK, I2S1_LRCK, SCP_SPI1_MO, + LVTS_SCK, DFD_TDO, dbg_mon_a1), + PIN(55, SPI5_MI, 0, 14, 0x23, 0x80, + SPI5_MI, I2S2_DI, I2S1_DO, SCP_SPI1_MI, + LVTS_SDO, DFD_TMS, dbg_mon_b32), + PIN(56, I2S1_DO, 0, 12, 0x25, 0x90, + I2S1_DO, I2S3_DO, RES3, RES4, + RES5, RES6, dbg_mon_a23), + PIN(57, I2S1_BCK, 0, 11, 0x25, 0x90, + I2S1_BCK, I2S3_BCK, RES3, RES4, + RES5, RES6, dbg_mon_a24), + PIN(58, I2S1_LRCK, 0, 13, 0x25, 0x90, + I2S1_LRCK, I2S3_LRCK, RES3, RES4, + RES5, RES6, dbg_mon_a25), + PIN(59, I2S1_MCK, 0, 14, 0x25, 0x90, + I2S1_MCK, I2S3_MCK, RES3, RES4, + RES5, RES6, dbg_mon_a27), + PIN(60, TDM_RX_LRCK, 0, 21, 0x23, 0x80, + TDM_RX_LRCK, ANT_SEL3, RES3, RES4, + CONN_MCU_DBGACK_N, RES6, RES7), + PIN(61, TDM_RX_BCK, 0, 16, 0x23, 0x80, + TDM_RX_BCK, ANT_SEL4, RES3, SPINOR_CK, + CONN_MCU_DBGI_N, RES6, RES7), + PIN(62, TDM_RX_MCLK, 0, 22, 0x23, 0x80, + TDM_RX_MCK, ANT_SEL5, RES3, SPINOR_CS, + CONN_MCU_TDI, RES6, RES7), + PIN(63, TDM_RX_DATA0, 0, 17, 0x23, 0x80, + TDM_RX_DATA0, ANT_SEL6, RES3, SPINOR_IO0, + CONN_MCU_TRST_B, RES6, RES7), + PIN(64, TDM_RX_DATA1, 0, 18, 0x23, 0x80, + TDM_RX_DATA1, ANT_SEL7, PWM0, SPINOR_IO1, + CONN_MCU_TCK, RES6, RES7), + PIN(65, TDM_RX_DATA2, 0, 19, 0x23, 0x80, + TDM_RX_DATA2, UCTS0, PWM1, SPINOR_IO2, + CONN_MCU_TDO, TP_UCTS1_AO, TP_UCTS2_AO), + PIN(66, TDM_RX_DATA3, 0, 20, 0x23, 0x80, + TDM_RX_DATA3, URTS0, PWM2, SPINOR_IO3, + CONN_MCU_TMS, TP_URTS1_AO, TP_URTS2_AO), + PIN(67, MSDC0_DSL, 1, 10, 0x21, 0x70, + MSDC0_DSL, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(68, MSDC0_CLK, 1, 0, 0x21, 0x70, + MSDC0_CLK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(69, MSDC0_CMD, 1, 1, 0x21, 0x70, + MSDC0_CMD, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(70, MSDC0_RSTB, 1, 11, 0x21, 0x70, + MSDC0_RSTB, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(71, MSDC0_DAT0, 1, 2, 0x21, 0x70, + MSDC0_DAT0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(72, MSDC0_DAT1, 1, 3, 0x21, 0x70, + MSDC0_DAT1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(73, MSDC0_DAT2, 1, 4, 0x21, 0x70, + MSDC0_DAT2, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(74, MSDC0_DAT3, 1, 5, 0x21, 0x70, + MSDC0_DAT3, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(75, MSDC0_DAT4, 1, 6, 0x21, 0x70, + MSDC0_DAT4, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(76, MSDC0_DAT5, 1, 7, 0x21, 0x70, + MSDC0_DAT5, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(77, MSDC0_DAT6, 1, 8, 0x21, 0x70, + MSDC0_DAT6, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(78, MSDC0_DAT7, 1, 9, 0x21, 0x70, + MSDC0_DAT7, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(79, KPCOL0, 1, 0, 0x25, 0x80, + KPCOL0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(80, KPCOL1, 1, 1, 0x25, 0x80, + KPCOL1, GPS_L1_ELNA_EN, PWM0, CLKM0, + RES5, RES6, RES7), + PIN(81, KPROW0, 1, 2, 0x25, 0x80, + KPROW0, RES2, PWM1, CLKM1, + RES5, RES6, RES7), + PIN(82, KPROW1, 1, 3, 0x25, 0x80, + KPROW1, RES2, PWM2, CLKM2, + RES5, RES6, RES7), + PIN(83, AP_GOOD, 0, 3, 0x16, 0x50, + AP_GOOD, GPS_PPS, RES3, EXT_FRAME_SYNC, + RES5, RES6, dbg_mon_a28), + PIN(84, MSDC1_CLK, 1, 0, 0x23, 0x70, + MSDC1_CLK, ADSP_JTAG_TCK, RES3, UDI_TCK, + CONN_DSP_JCK, SSPM_JTAG_TCK, DFD_TCK_XI), + PIN(85, MSDC1_CMD, 1, 1, 0x23, 0x70, + MSDC1_CMD, ADSP_JTAG_TMS, CONN_MCU_AICE_TMSC, UDI_TMS, + CONN_DSP_JMS, SSPM_JTAG_TMS, DFD_TMS), + PIN(86, MSDC1_DAT0, 1, 2, 0x23, 0x70, + MSDC1_DAT0, ADSP_JTAG_TDI, RES3, UDI_TDI, + CONN_DSP_JDI, SSPM_JTAG_TDI, DFD_TDI), + PIN(87, MSDC1_DAT1, 1, 3, 0x23, 0x70, + MSDC1_DAT1, ADSP_JTAG_TDO, RES3, UDI_TDO, + CONN_DSP_JDO, SSPM_JTAG_TDO, DFD_TDO), + PIN(88, MSDC1_DAT2, 1, 4, 0x23, 0x70, + MSDC1_DAT2, ADSP_JTAG_TRSTN, CONN_MCU_AICE_TCKC, UDI_NTRST, + CONN_WIFI_TXD, SSPM_JTAG_TRSTN, RES7), + PIN(89, MSDC1_DAT3, 1, 5, 0x23, 0x70, + MSDC1_DAT3, RES2, RES3, RES4, + CONN_DSP_JINTP, RES6, RES7), + PIN(90, IDDIG_P0, 0, 2, 0x23, 0x80, + IDDIG_P0, RES2, RES3, PGD_HV_HSC_PWR4, + GDU_SUM_TROOP2_2, RES6, RES7), + PIN(91, USB_DRVVBUS_P0, 0, 23, 0x23, 0x80, + USB_DRVVBUS_P0, RES2, RES3, PGD_HV_HSC_PWR5, + GDU_TROOPS_DET0, RES6, RES7), + PIN(92, VBUS_VALID_P0, 0, 25, 0x23, 0x80, + VBUS_VALID_P0, RES2, RES3, PGD_DA_EFUSE_RDY, + GDU_TROOPS_DET1, RES6, RES7), + PIN(93, IDDIG_P1, 0, 3, 0x23, 0x80, + IDDIG_P1, PWM0, CLKM0, PGD_DA_EFUSE_RDY_PRE, + GDU_TROOPS_DET2, RES6, RES7), + PIN(94, USB_DRVVBUS_P1, 0, 24, 0x23, 0x80, + USB_DRVVBUS_P1, PWM1, CLKM1, PGD_DA_PWRGD_RESET, + RES5, RES6, RES7), + PIN(95, VBUS_VALID_P1, 0, 26, 0x23, 0x80, + VBUS_VALID_P1, PWM2, CLKM2, PGD_DA_PWRGD_ENB, + RES5, RES6, RES7), + PIN(96, DSI_TE, 0, 1, 0x12, 0x60, + DSI_TE, RES2, RES3, RES4, + RES5, RES6, dbg_mon_a29), + PIN(97, DISP_PWM, 0, 0, 0x12, 0x60, + DISP_PWM, RES2, RES3, RES4, + RES5, RES6, dbg_mon_a30), + PIN(98, LCM_RST, 0, 2, 0x12, 0x60, + LCM_RST, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(99, DPI_PCLK, 0, 14, 0x24, 0x60, + DPI_PCLK, GPS_L1_ELNA_EN, SSPM_JTAG_TCK, RES4, + ANT_SEL0, TP_GPIO0_AO, PGD_LV_LSC_PWR0), + PIN(100, DPI_VSYNC, 0, 15, 0x24, 0x60, + DPI_VSYNC, KPCOL2, SSPM_JTAG_TMS, RES4, + ANT_SEL1, TP_GPIO1_AO, PGD_LV_LSC_PWR1), + PIN(101, DPI_HSYNC, 0, 13, 0x24, 0x60, + DPI_HSYNC, KPROW2, SSPM_JTAG_TDI, RES4, + ANT_SEL2, TP_GPIO2_AO, PGD_LV_LSC_PWR2), + PIN(102, DPI_DE, 0, 12, 0x24, 0x60, + DPI_DE, RES2, SSPM_JTAG_TDO, RES4, + ANT_SEL3, TP_GPIO3_AO, PGD_LV_LSC_PWR3), + PIN(103, DPI_DATA0, 0, 0, 0x24, 0x60, + DPI_DATA0, RES2, SSPM_JTAG_TRSTN, CLKM0, + ANT_SEL4, TP_GPIO4_AO, PGD_LV_LSC_PWR4), + PIN(104, DPI_DATA1, 0, 1, 0x24, 0x60, + DPI_DATA1, GPS_PPS, UCTS2, CLKM1, + ANT_SEL5, TP_GPIO5_AO, PGD_LV_LSC_PWR5), + PIN(105, DPI_DATA2, 0, 4, 0x24, 0x60, + DPI_DATA2, CONN_TCXOENA_REQ, URTS2, CLKM2, + ANT_SEL6, TP_GPIO6_AO, PGD_LV_HSC_PWR0), + PIN(106, DPI_DATA3, 0, 5, 0x24, 0x60, + DPI_DATA3, TP_UTXD1_AO, UTXD2, PWM0, + ANT_SEL7, TP_GPIO7_AO, PGD_LV_HSC_PWR1), + PIN(107, DPI_DATA4, 0, 6, 0x24, 0x60, + DPI_DATA4, TP_URXD1_AO, URXD2, PWM1, + RES5, GDU_SUM_TROOP0_0, PGD_LV_HSC_PWR2), + PIN(108, DPI_DATA5, 0, 7, 0x24, 0x60, + DPI_DATA5, TP_UCTS1_AO, UCTS0, PWM2, + RES5, GDU_SUM_TROOP0_1, PGD_LV_HSC_PWR3), + PIN(109, DPI_DATA6, 0, 8, 0x24, 0x60, + DPI_DATA6, TP_URTS1_AO, URTS0, I2S0_DI, + I2S2_DI, GDU_SUM_TROOP0_2, PGD_LV_HSC_PWR4), + PIN(110, DPI_DATA7, 0, 9, 0x24, 0x60, + DPI_DATA7, TP_UCTS2_AO, UCTS1, I2S3_BCK, + I2S1_BCK, GDU_SUM_TROOP1_0, PGD_LV_HSC_PWR5), + PIN(111, DPI_DATA8, 0, 10, 0x24, 0x60, + DPI_DATA8, TP_URTS2_AO, URTS1, I2S3_MCK, + I2S1_MCK, GDU_SUM_TROOP1_1, PGD_HV_HSC_PWR0), + PIN(112, DPI_DATA9, 0, 11, 0x24, 0x60, + DPI_DATA9, TP_URXD2_AO, URXD1, I2S3_LRCK, + I2S1_LRCK, GDU_SUM_TROOP1_2, PGD_HV_HSC_PWR1), + PIN(113, DPI_DATA10, 0, 2, 0x24, 0x60, + DPI_DATA10, TP_UTXD2_AO, UTXD1, I2S3_DO, + I2S1_DO, GDU_SUM_TROOP2_0, PGD_HV_HSC_PWR2), + PIN(114, DPI_DATA11, 0, 3, 0x24, 0x60, + DPI_DATA11, RES2, RES3, RES4, + RES5, GDU_SUM_TROOP2_1, PGD_HV_HSC_PWR3), + PIN(115, PCM_CLK, 0, 4, 0x23, 0x80, + PCM_CLK, I2S0_BCK, I2S2_BCK, RES4, + RES5, RES6, RES7), + PIN(116, PCM_SYNC, 0, 7, 0x23, 0x80, + PCM_SYNC, I2S0_LRCK, I2S2_LRCK, RES4, + RES5, RES6, RES7), + PIN(117, PCM_DI, 0, 5, 0x23, 0x80, + PCM_DI, I2S0_DI, I2S2_DI, RES4, + RES5, RES6, RES7), + PIN(118, PCM_DO, 0, 6, 0x23, 0x80, + PCM_DO, I2S0_MCK, I2S2_MCK, I2S3_DO, + I2S1_DO, RES6, RES7), + PIN(119, JTMS_SEL1, 0, 22, 0x25, 0x90, + JTMS_SEL1, UDI_TMS, DFD_TMS, SPM_JTAG_TMS, + SCP_JTAG_TMS, ADSP_JTAG_TMS, RES7), + PIN(120, JTCK_SEL1, 0, 19, 0x25, 0x90, + JTCK_SEL1, UDI_TCK, DFD_TCK_XI, SPM_JTAG_TCK, + SCP_JTAG_TCK, ADSP_JTAG_TCK, RES7), + PIN(121, JTDI_SEL1, 0, 20, 0x25, 0x90, + JTDI_SEL1, UDI_TDI, DFD_TDI, SPM_JTAG_TDI, + SCP_JTAG_TDI, ADSP_JTAG_TDI, RES7), + PIN(122, JTDO_SEL1, 0, 21, 0x25, 0x90, + JTDO_SEL1, UDI_TDO, DFD_TDO, SPM_JTAG_TDO, + SCP_JTAG_TDO, ADSP_JTAG_TDO, RES7), + PIN(123, JTRSTN_SEL1, 0, 23, 0x25, 0x90, + JTRSTN_SEL1, UDI_NTRST, RES3, SPM_JTAG_TRSTN, + SCP_JTAG_TRSTN, ADSP_JTAG_TRSTN, RES7), + PIN(124, CAM_CLK0, 0, 0, 0x25, 0x90, + CMMCLK0, CLKM0, PWM0, RES4, + RES5, RES6, RES7), + PIN(125, CAM_CLK1, 0, 1, 0x25, 0x90, + CMMCLK1, CLKM1, PWM1, RES4, + RES5, RES6, dbg_mon_b0), + PIN(126, CAM_CLK2, 0, 2, 0x25, 0x90, + CMMCLK2, CLKM2, PWM2, RES4, + RES5, RES6, dbg_mon_b1), + PIN(127, SCL0, 0, 8, 0x23, 0x80, + SCL0, RES2, RES3, SCP_SCL0, + SCP_SCL1, RES6, RES7), + PIN(128, SDA0, 0, 10, 0x23, 0x80, + SDA0, RES2, RES3, SCP_SDA0, + SCP_SDA1, RES6, RES7), + PIN(129, SCL1, 0, 24, 0x25, 0x90, + SCL1, RES2, RES3, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b4), + PIN(130, SDA1, 0, 26, 0x25, 0x90, + SDA1, RES2, RES3, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b5), + PIN(131, SCL2, 0, 25, 0x25, 0x90, + SCL2, SSPM_UTXD_AO, CONN_UART0_TXD, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b6), + PIN(132, SDA2, 0, 27, 0x25, 0x90, + SDA2, SSPM_URXD_AO, CONN_UART0_RXD, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b7), + PIN(133, SCL3, 0, 9, 0x21, 0x80, + SCL3, RES2, RES3, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b8), + PIN(134, SDA3, 0, 12, 0x21, 0x80, + SDA3, RES2, GPS_PPS, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b9), + PIN(135, SCL4, 0, 21, 0x16, 0x50, + SCL4, TP_UTXD1_AO, UTXD1, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b10), + PIN(136, SDA4, 0, 24, 0x16, 0x50, + SDA4, TP_URXD1_AO, URXD1, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b11), + PIN(137, SCL5, 0, 10, 0x21, 0x80, + SCL5, UTXD2, UCTS1, SCP_SCL0, + SCP_SCL1, RES6, RES7), + PIN(138, SDA5, 0, 13, 0x21, 0x80, + SDA5, URXD2, URTS1, SCP_SDA0, + SCP_SDA1, RES6, RES7), + PIN(139, SCL6, 0, 7, 0x12, 0x60, + SCL6, UTXD1, TP_UTXD1_AO, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b12), + PIN(140, SDA6, 0, 8, 0x12, 0x60, + SDA6, URXD1, TP_URXD1_AO, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b13), + PIN(141, SCL7, 0, 9, 0x23, 0x80, + SCL7, URTS0, TP_URTS1_AO, SCP_SCL0, + SCP_SCL1, UDI_TCK, dbg_mon_b14), + PIN(142, SDA7, 0, 11, 0x23, 0x80, + SDA7, UCTS0, TP_UCTS1_AO, SCP_SDA0, + SCP_SDA1, RES6, RES7), + PIN(143, SCL8, 0, 22, 0x16, 0x50, + SCL8, RES2, RES3, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b16), + PIN(144, SDA8, 0, 25, 0x16, 0x50, + SDA8, RES2, RES3, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b17), + PIN(145, SCL9, 0, 23, 0x16, 0x50, + SCL9, CMVREF1, GPS_PPS, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b18), + PIN(146, SDA9, 0, 26, 0x16, 0x50, + SDA9, CMVREF0, RES3, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b19), + PIN(147, PERIPHERAL_EN0, 0, 23, 0x24, 0x60, + CMFLASH0, LVTS_SDI, DPI_DATA12, TP_GPIO0_AO, + ANT_SEL3, DFD_TCK_XI, dbg_mon_b20), + PIN(148, PERIPHERAL_EN1, 0, 24, 0x24, 0x60, + CMFLASH1, LVTS_SCF, DPI_DATA13, TP_GPIO1_AO, + ANT_SEL4, DFD_TMS, dbg_mon_b21), + PIN(149, PERIPHERAL_EN2, 0, 25, 0x24, 0x60, + CMFLASH2, CLKM0, DPI_DATA14, TP_GPIO2_AO, + ANT_SEL5, DFD_TDI, dbg_mon_b22), + PIN(150, PERIPHERAL_EN3, 0, 26, 0x24, 0x60, + RES1, CLKM1, DPI_DATA15, TP_GPIO3_AO, + ANT_SEL6, DFD_TDO, dbg_mon_b23), + PIN(151, PERIPHERAL_EN4, 0, 27, 0x24, 0x60, + GPS_L1_ELNA_EN, CLKM2, DPI_DATA16, TP_GPIO4_AO, + ANT_SEL7, UDI_TMS, dbg_mon_b24), + PIN(152, PERIPHERAL_EN5, 0, 28, 0x24, 0x60, + RES1, CLKM3, DPI_DATA17, TP_GPIO5_AO, + RES5, RES6, RES7), + PIN(153, PERIPHERAL_EN6, 0, 29, 0x24, 0x60, + CONN_TCXOENA_REQ, RES2, DPI_DATA18, TP_GPIO6_AO, + RES5, UDI_TDI, dbg_mon_b26), + PIN(154, PERIPHERAL_EN7, 0, 30, 0x24, 0x60, + PWM0, CMVREF2, DPI_DATA19, TP_GPIO7_AO, + RES5, UDI_TDO, dbg_mon_b27), + PIN(155, PERIPHERAL_EN8, 0, 31, 0x24, 0x60, + PWM1, CMVREF1, DPI_DATA20, RES4, + RES5, UDI_NTRST, dbg_mon_b28), + PIN(156, PERIPHERAL_EN9, 0, 0, 0x24, 0x70, + PWM2, CMVREF0, DPI_DATA21, RES4, + RES5, RES6, RES7), + PIN(157, PWRAP_SPI0_CSN, 0, 4, 0x12, 0x60, + PWRAP_SPI0_CSN, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(158, PWRAP_SPI0_CK, 0, 3, 0x12, 0x60, + PWRAP_SPI0_CK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(159, PWRAP_SPI0_MO, 0, 6, 0x12, 0x60, + PWRAP_SPI0_MO, PWRAP_SPI0_MI, RES3, RES4, + RES5, RES6, RES7), + PIN(160, PWRAP_SPI0_MI, 0, 5, 0x12, 0x60, + PWRAP_SPI0_MI, PWRAP_SPI0_MO, RES3, RES4, + RES5, RES6, RES7), + PIN(161, SRCLKENA0, 0, 23, 0x12, 0x60, + SRCLKENA0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(162, SRCLKENA1, 0, 24, 0x12, 0x60, + SRCLKENA1, RES2, RES3, RES4, + RES5, RES6, dbg_mon_a31), + PIN(163, SCP_VREQ_VAO, 0, 11, 0x21, 0x80, + SCP_VREQ_VAO, DVFSRC_EXT_REQ, RES3, RES4, + RES5, RES6, RES7), + PIN(164, RTC32K_CK, 0, 8, 0x21, 0x80, + RTC32K_CK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(165, WATCHDOG, 0, 16, 0x21, 0x80, + WATCHDOG, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(166, AUD_CLK_MOSI, 0, 1, 0x21, 0x80, + AUD_CLK_MOSI, AUD_CLK_MISO, I2S1_MCK, RES4, + RES5, RES6, RES7), + PIN(167, AUD_SYNC_MOSI, 0, 7, 0x21, 0x80, + AUD_SYNC_MOSI, AUD_SYNC_MISO, I2S1_BCK, RES4, + RES5, RES6, RES7), + PIN(168, AUD_DAT_MOSI0, 0, 4, 0x21, 0x80, + AUD_DAT_MOSI0, AUD_DAT_MISO0, I2S1_LRCK, RES4, + RES5, RES6, RES7), + PIN(169, AUD_DAT_MOSI1, 0, 5, 0x21, 0x80, + AUD_DAT_MOSI1, AUD_DAT_MISO1, I2S1_DO, RES4, + RES5, RES6, RES7), + PIN(170, AUD_CLK_MISO, 0, 0, 0x21, 0x80, + AUD_CLK_MISO, AUD_CLK_MOSI, I2S2_MCK, RES4, + RES5, RES6, RES7), + PIN(171, AUD_SYNC_MISO, 0, 6, 0x21, 0x80, + AUD_SYNC_MISO, AUD_SYNC_MOSI, I2S2_BCK, RES4, + RES5, RES6, RES7), + PIN(172, AUD_DAT_MISO0, 0, 2, 0x21, 0x80, + AUD_DAT_MISO0, AUD_DAT_MOSI0, I2S2_LRCK, VOW_DAT_MISO, + RES5, RES6, RES7), + PIN(173, AUD_DAT_MISO1, 0, 3, 0x21, 0x80, + AUD_DAT_MISO1, AUD_DAT_MOSI1, I2S2_DI, VOW_CLK_MISO, + RES5, RES6, RES7), + PIN(174, CONN_TOP_CLK, 0, 7, 0x16, 0x50, + CONN_TOP_CLK, AUXIF_CLK, DFD_TCK_XI, RES4, + RES5, RES6, dbg_mon_b3), + PIN(175, CONN_TOP_DATA, 0, 8, 0x16, 0x50, + CONN_TOP_DATA, AUXIF_ST, DFD_TMS, RES4, + RES5, RES6, dbg_mon_b15), + PIN(176, CONN_BT_CLK, 0, 4, 0x16, 0x50, + CONN_BT_CLK, RES2, DFD_TDI, RES4, + RES5, RES6, dbg_mon_b2), + PIN(177, CONN_BT_DATA, 0, 5, 0x16, 0x50, + CONN_BT_DATA, RES2, DFD_TDO, RES4, + RES5, RES6, RES7), + PIN(178, CONN_HRST_B, 0, 6, 0x16, 0x50, + CONN_HRST_B, RES2, UDI_TMS, RES4, + RES5, RES6, dbg_mon_b25), + PIN(179, CONN_WB_PTA, 0, 9, 0x16, 0x50, + CONN_WB_PTA, RES2, UDI_TCK, RES4, + RES5, RES6, dbg_mon_b29), + PIN(180, CONN_WF_CTRL0, 0, 10, 0x16, 0x50, + CONN_WF_CTRL0, RES2, UDI_TDI, RES4, + RES5, RES6, RES7), + PIN(181, CONN_WF_CTRL1, 0, 11, 0x16, 0x50, + CONN_WF_CTRL1, RES2, UDI_TDO, RES4, + RES5, RES6, RES7), + PIN(182, CONN_WF_CTRL2, 0, 12, 0x16, 0x50, + CONN_WF_CTRL2, RES2, UDI_NTRST, RES4, + RES5, RES6, RES7), + PIN(183, SPMI_SCL, 0, 21, 0x12, 0x60, + SPMI_SCL, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(184, SPMI_SDA, 0, 22, 0x12, 0x60, + SPMI_SDA, RES2, RES3, RES4, + RES5, RES6, RES7), +}; + +struct val_regs { + uint32_t val; + uint32_t set; + uint32_t rst; + uint32_t align; +}; + +struct gpio_regs { + struct val_regs dir[7]; + uint8_t rsv00[144]; + struct val_regs dout[7]; + uint8_t rsv01[144]; + struct val_regs din[7]; + uint8_t rsv02[144]; + struct val_regs mode[28]; + uint8_t rsv03[560]; + uint32_t dram_pinmux_trapping; +}; + +check_member(gpio_regs, mode[27].val, 0x4b0); +check_member(gpio_regs, dram_pinmux_trapping, 0x6f0); + +static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE); + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/gpio_base.h b/src/soc/mediatek/mt8186/include/soc/gpio_base.h new file mode 100644 index 0000000..7f6480a --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/gpio_base.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.1 + */ + +#ifndef SOC_MEDIATEK_MT8186_GPIO_BASE_H +#define SOC_MEDIATEK_MT8186_GPIO_BASE_H + +#include <stdint.h> + +typedef union { + u32 raw; + struct { + u32 id : 8; + u32 flag : 3; + u32 bit : 5; + u32 base : 8; + u32 offset : 8; + }; +} gpio_t; + +#endif 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee Gerrit-Change-Number: 58836 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/trogdor: Mark kingoftown as supporting Parade PS84640
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58789 ) Change subject: mb/google/trogdor: Mark kingoftown as supporting Parade PS84640 ...................................................................... mb/google/trogdor: Mark kingoftown as supporting Parade PS84640 BUG=b:204272905 BRANCH=master TEST=emerge-trogdor coreboot Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Change-Id: Ie13ddfef6adfd53adb0a0d3a98995fb00b8a45e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58789 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philip Chen <philipchen(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/trogdor/mainboard.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Philip Chen: Looks good to me, approved diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index f007f45..1a60131 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -83,7 +83,8 @@ */ return (CONFIG(BOARD_GOOGLE_HOMESTAR) && board_id() >= 4 && board_id() != 19 && board_id() != 23) || - (CONFIG(BOARD_GOOGLE_LAZOR) && board_id() >= 9); + (CONFIG(BOARD_GOOGLE_LAZOR) && board_id() >= 9) || + (CONFIG(BOARD_GOOGLE_KINGOFTOWN) && board_id() >= 1); } static void power_on_sn65dsi86_bridge(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/58789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie13ddfef6adfd53adb0a0d3a98995fb00b8a45e6 Gerrit-Change-Number: 58789 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Nick Vaccaro (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Reka Norman, Sridhar Siricilla, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58679 ) Change subject: util/spd_tools: Add LP5 support for ADL ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Gerrit-Change-Number: 58679 Gerrit-PatchSet: 8 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:56:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: move SGX ACPI code to block/acpi
by Michael Niewöhner (Code Review) 03 Nov '21

03 Nov '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58925 ) Change subject: soc/intel: move SGX ACPI code to block/acpi ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/58925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I089d0ee97c37df2be060b5996183201bfa9b49ca Gerrit-Change-Number: 58925 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:56:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: generate SSDT instead of using GNVS for SGX
by Michael Niewöhner (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Felix Singer, Pratik Prajapati, Nico Huber, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Andrey Petrov, Kyösti Mälkki, Patrick Rudolph, Pratikkumar V Prajapati. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58394 ) Change subject: soc/intel: generate SSDT instead of using GNVS for SGX ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/sgx/sgx.c: https://review.coreboot.org/c/coreboot/+/58394/comment/edfab532_e9697439 PS3, Line 273: } > Sorry, that was meant in local context. I mean […] done CB:58925 -- To view, visit https://review.coreboot.org/c/coreboot/+/58394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf9f035e0c2b8617eef82fb043293bcb913e3012 Gerrit-Change-Number: 58394 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:55:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Initialize watchdog
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58835 ) Change subject: soc/mediatek/mt8186: Initialize watchdog ...................................................................... soc/mediatek/mt8186: Initialize watchdog MT8186 requires writing speical value to mode register to clear status register. The flow of clear status is different from other platforms, so we override mtk_wdt_clr_status() for MT8186. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I290b69573a8e58db76814e16b5c17c23413f1108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58835 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8186/Kconfig M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/bootblock.c A src/soc/mediatek/mt8186/wdt.c 4 files changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig index 28589e3..9fa391a 100644 --- a/src/soc/mediatek/mt8186/Kconfig +++ b/src/soc/mediatek/mt8186/Kconfig @@ -6,6 +6,7 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 select HAVE_UART_SPECIAL + select SOC_MEDIATEK_COMMON if SOC_MEDIATEK_MT8186 diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index c9cb305..72d67cc 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -5,22 +5,26 @@ bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c +bootblock-y += ../common/wdt.c wdt.c verstage-$(CONFIG_SPI_FLASH) += spi.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c +verstage-y += ../common/wdt.c wdt.c romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c +romstage-y += ../common/wdt.c wdt.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c +ramstage-y += ../common/wdt.c wdt.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8186/bootblock.c b/src/soc/mediatek/mt8186/bootblock.c index f48e78c..770c603 100644 --- a/src/soc/mediatek/mt8186/bootblock.c +++ b/src/soc/mediatek/mt8186/bootblock.c @@ -2,8 +2,10 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> +#include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); + mtk_wdt_init(); } diff --git a/src/soc/mediatek/mt8186/wdt.c b/src/soc/mediatek/mt8186/wdt.c new file mode 100644 index 0000000..d0e13d9 --- /dev/null +++ b/src/soc/mediatek/mt8186/wdt.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.4 + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/wdt.h> + +#define MTK_WDT_CLR_STATUS 0x22000000 + +void mtk_wdt_clr_status(uint32_t wdt_sta) +{ + write32(&mtk_wdt->wdt_mode, wdt_sta | MTK_WDT_CLR_STATUS); +} 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I290b69573a8e58db76814e16b5c17c23413f1108 Gerrit-Change-Number: 58835 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: Add an overridable function for WDT clear status
by Felix Held (Code Review) 03 Nov '21

03 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58834 ) Change subject: soc/mediatek: Add an overridable function for WDT clear status ...................................................................... soc/mediatek: Add an overridable function for WDT clear status mtk_wdt_clr_status is different for MT8186 and MT8195, so we move this function to soc folder. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/Kconfig M src/soc/mediatek/common/include/soc/wdt.h M src/soc/mediatek/common/wdt.c M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/wdt.c 6 files changed, 20 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index 754c0da..b581ffb 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -29,11 +29,6 @@ This option enables memory basic compare test to verify the DRAM read or write is as expected. -config CLEAR_WDT_MODE_REG - bool - help - Enable this option to clear WTD mode register explicitly. - config DPM_FOUR_CHANNEL bool default n diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h index 5847d495..6b27bef 100644 --- a/src/soc/mediatek/common/include/soc/wdt.h +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -21,7 +21,6 @@ /* WDT_MODE */ enum { MTK_WDT_MODE_KEY = 0x22000000, - MTK_WDT_CLR_STATUS = 0x230001FF, MTK_WDT_MODE_DUAL_MODE = 1 << 6, MTK_WDT_MODE_IRQ = 1 << 3, MTK_WDT_MODE_EXTEN = 1 << 2, @@ -40,5 +39,6 @@ static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE; int mtk_wdt_init(void); +void mtk_wdt_clr_status(uint32_t wdt_sta); #endif /* SOC_MEDIATEK_COMMON_WDT_H */ diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 05bd27d..b228e56 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -5,6 +5,8 @@ #include <soc/wdt.h> #include <vendorcode/google/chromeos/chromeos.h> +__weak void mtk_wdt_clr_status(uint32_t wdt_sta) { /* do nothing */ } + int mtk_wdt_init(void) { uint32_t wdt_sta; @@ -12,8 +14,7 @@ /* Writing mode register will clear status register */ wdt_sta = read32(&mtk_wdt->wdt_status); - if (CONFIG(CLEAR_WDT_MODE_REG)) - write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS); + mtk_wdt_clr_status(wdt_sta); printk(BIOS_INFO, "WDT: Last reset was "); if (wdt_sta & MTK_WDT_STA_HW_RST) { diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig index df1b5d8..b96ccd8 100644 --- a/src/soc/mediatek/mt8195/Kconfig +++ b/src/soc/mediatek/mt8195/Kconfig @@ -9,7 +9,6 @@ select CACHE_MRC_SETTINGS select HAVE_UART_SPECIAL select SOC_MEDIATEK_COMMON - select CLEAR_WDT_MODE_REG select DPM_FOUR_CHANNEL if SOC_MEDIATEK_MT8195 diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index f99fa33..c362899 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -11,7 +11,7 @@ bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c bootblock-y += ../common/uart.c -bootblock-y += ../common/wdt.c +bootblock-y += ../common/wdt.c wdt.c verstage-y += ../common/auxadc.c verstage-y += ../common/flash_controller.c @@ -20,7 +20,7 @@ verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c verstage-y += ../common/uart.c -verstage-y += ../common/wdt.c +verstage-y += ../common/wdt.c wdt.c ramstage-y += apusys.c romstage-y += ../common/auxadc.c @@ -40,7 +40,7 @@ romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c -romstage-y += ../common/wdt.c +romstage-y += ../common/wdt.c wdt.c romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif_spi.c pmif_spi.c romstage-y += ../common/pmif_spmi.c pmif_spmi.c @@ -79,7 +79,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/ufs.c ramstage-y += ../common/usb.c usb.c -ramstage-y += ../common/wdt.c +ramstage-y += ../common/wdt.c wdt.c BL31_MAKEARGS += PLAT=mt8195 diff --git a/src/soc/mediatek/mt8195/wdt.c b/src/soc/mediatek/mt8195/wdt.c new file mode 100644 index 0000000..c000bf7 --- /dev/null +++ b/src/soc/mediatek/mt8195/wdt.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/wdt.h> + +#define MTK_WDT_CLR_STATUS 0x230001FF + +void mtk_wdt_clr_status(uint32_t wdt_sta) +{ + write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/58834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e Gerrit-Change-Number: 58834 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Tim Wawrzynczak (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Reka Norman, Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58679 ) Change subject: util/spd_tools: Add LP5 support for ADL ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > That's a good point. […] The lp4x SPD tools support Cezanne (AMD) as well, and the ddr4 tools support Picasso (AMD) too, so the goal is to try and make a tool that can produce SPDs for different chipsets. It would be instructive I'm sure to see AMD's MRC requirements for LP5 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/58679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Gerrit-Change-Number: 58679 Gerrit-PatchSet: 8 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:49:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Nick Vaccaro (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Tim Wawrzynczak, Reka Norman, Sridhar Siricilla, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58679 ) Change subject: util/spd_tools: Add LP5 support for ADL ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > It’s been bothering me how ADL-specific this implementation is. E.g. […] That's a good point. Given the spd tools are currently (AFAIK) customized around intel requirements, we probably should make that differentiation, perhaps move the current contents of util/spd_tools/src/ to util/spd_tools/src/intel/? Has the spd tool been used with AMD platforms, or just Intel? I'm not sure how different AMD requirements are. re: "wait and see what other platforms do, and generalise the code as needed then" I would agree that we should wait to add features until they are needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/58679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Gerrit-Change-Number: 58679 Gerrit-PatchSet: 8 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:46:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Tim Wawrzynczak (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Reka Norman, Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58679 ) Change subject: util/spd_tools: Add LP5 support for ADL ...................................................................... Patch Set 8: Code-Review+1 (4 comments) Patchset: PS8: > It’s been bothering me how ADL-specific this implementation is. E.g. […] I completely agree with your assessment Reka. This is the first platform we're supporting LP5 on, so we may have to make some tweaks in the future depending on other vendors or chipsets. This is the approach to make things the most generally applicable for all chipsets. File util/spd_tools/src/spd_gen/lp5.go: https://review.coreboot.org/c/coreboot/+/58679/comment/d8481997_3f24b8b1 PS5, Line 456: ok == false nit: I think the convention is `; !ok {` https://review.coreboot.org/c/coreboot/+/58679/comment/dce75c7b_9ab51db6 PS5, Line 484: ; ok == false `; !ok {` File util/spd_tools/src/spd_gen/lp5.go: https://review.coreboot.org/c/coreboot/+/58679/comment/61050676_83672385 PS8, Line 603: k == false nit: `!ok` -- To view, visit https://review.coreboot.org/c/coreboot/+/58679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Gerrit-Change-Number: 58679 Gerrit-PatchSet: 8 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 18:42:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2021