Change in coreboot[master]: soc/mediatek: Add an overridable function for WDT clear status

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58834 )

Change subject: soc/mediatek: Add an overridable function for WDT clear status
......................................................................

soc/mediatek: Add an overridable function for WDT clear status

mtk_wdt_clr_status is different for MT8186 and MT8195,
so we move this function to soc folder.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen 
Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834
Reviewed-by: Rex-BC Chen 
Reviewed-by: Yu-Ping Wu 
Tested-by: build bot (Jenkins) 
---
M src/soc/mediatek/common/Kconfig
M src/soc/mediatek/common/include/soc/wdt.h
M src/soc/mediatek/common/wdt.c
M src/soc/mediatek/mt8195/Kconfig
M src/soc/mediatek/mt8195/Makefile.inc
A src/soc/mediatek/mt8195/wdt.c
6 files changed, 20 insertions(+), 13 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved
  Rex-BC Chen: Looks good to me, but someone else must approve

diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig
index 754c0da..b581ffb 100644
--- a/src/soc/mediatek/common/Kconfig
+++ b/src/soc/mediatek/common/Kconfig
@@ -29,11 +29,6 @@
      This option enables memory basic compare test to verify the DRAM read
      or write is as expected.

-config CLEAR_WDT_MODE_REG
-	bool
-	help
-	  Enable this option to clear WTD mode register explicitly.
-
 config DPM_FOUR_CHANNEL
    bool
    default n
diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h
index 5847d495..6b27bef 100644
--- a/src/soc/mediatek/common/include/soc/wdt.h
+++ b/src/soc/mediatek/common/include/soc/wdt.h
@@ -21,7 +21,6 @@
 /* WDT_MODE */
 enum {
    MTK_WDT_MODE_KEY	= 0x22000000,
-	MTK_WDT_CLR_STATUS	= 0x230001FF,
    MTK_WDT_MODE_DUAL_MODE	= 1 << 6,
    MTK_WDT_MODE_IRQ	= 1 << 3,
    MTK_WDT_MODE_EXTEN	= 1 << 2,
@@ -40,5 +39,6 @@
 static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE;

int mtk_wdt_init(void);
+void mtk_wdt_clr_status(uint32_t wdt_sta);

#endif /* SOC_MEDIATEK_COMMON_WDT_H */
diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c
index 05bd27d..b228e56 100644
--- a/src/soc/mediatek/common/wdt.c
+++ b/src/soc/mediatek/common/wdt.c
@@ -5,6 +5,8 @@
 #include <soc/wdt.h>
 #include <vendorcode/google/chromeos/chromeos.h>

+__weak void mtk_wdt_clr_status(uint32_t wdt_sta) { /* do nothing */ }
+
 int mtk_wdt_init(void)
 {
    uint32_t wdt_sta;
@@ -12,8 +14,7 @@
    /* Writing mode register will clear status register */
    wdt_sta = read32(&mtk_wdt->wdt_status);

-	if (CONFIG(CLEAR_WDT_MODE_REG))
-		write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS);
+	mtk_wdt_clr_status(wdt_sta);

printk(BIOS_INFO, "WDT: Last reset was ");
    if (wdt_sta & MTK_WDT_STA_HW_RST) {
diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig
index df1b5d8..b96ccd8 100644
--- a/src/soc/mediatek/mt8195/Kconfig
+++ b/src/soc/mediatek/mt8195/Kconfig
@@ -9,7 +9,6 @@
    select CACHE_MRC_SETTINGS
    select HAVE_UART_SPECIAL
    select SOC_MEDIATEK_COMMON
-	select CLEAR_WDT_MODE_REG
    select DPM_FOUR_CHANNEL

if SOC_MEDIATEK_MT8195
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index f99fa33..c362899 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -11,7 +11,7 @@
 bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 bootblock-y += ../common/timer.c timer.c
 bootblock-y += ../common/uart.c
-bootblock-y += ../common/wdt.c
+bootblock-y += ../common/wdt.c wdt.c

verstage-y += ../common/auxadc.c
 verstage-y += ../common/flash_controller.c
@@ -20,7 +20,7 @@
 verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 verstage-y += ../common/timer.c timer.c
 verstage-y += ../common/uart.c
-verstage-y += ../common/wdt.c
+verstage-y += ../common/wdt.c wdt.c

ramstage-y += apusys.c
 romstage-y += ../common/auxadc.c
@@ -40,7 +40,7 @@
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 romstage-y += ../common/timer.c timer.c
 romstage-y += ../common/uart.c
-romstage-y += ../common/wdt.c
+romstage-y += ../common/wdt.c wdt.c
 romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
 romstage-y += ../common/pmif_spmi.c pmif_spmi.c
@@ -79,7 +79,7 @@
 ramstage-y += ../common/uart.c
 ramstage-y += ../common/ufs.c
 ramstage-y += ../common/usb.c usb.c
-ramstage-y += ../common/wdt.c
+ramstage-y += ../common/wdt.c wdt.c

BL31_MAKEARGS += PLAT=mt8195

diff --git a/src/soc/mediatek/mt8195/wdt.c b/src/soc/mediatek/mt8195/wdt.c
new file mode 100644
index 0000000..c000bf7
--- /dev/null
+++ b/src/soc/mediatek/mt8195/wdt.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/wdt.h>
+
+#define MTK_WDT_CLR_STATUS 0x230001FF
+
+void mtk_wdt_clr_status(uint32_t wdt_sta)
+{
+	write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS);
+}