coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/baytrail: Make `num_cpus` unsigned
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58916 ) Change subject: soc/intel/baytrail: Make `num_cpus` unsigned ...................................................................... soc/intel/baytrail: Make `num_cpus` unsigned Change-Id: I9ab0106c27a834d5d2ac1cb8023f4400a8ad91cd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/include/soc/pattrs.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/58916/1 diff --git a/src/soc/intel/baytrail/include/soc/pattrs.h b/src/soc/intel/baytrail/include/soc/pattrs.h index cd22e12..d0d3bf0 100644 --- a/src/soc/intel/baytrail/include/soc/pattrs.h +++ b/src/soc/intel/baytrail/include/soc/pattrs.h @@ -29,7 +29,7 @@ int stepping; const void *microcode_patch; int address_bits; - int num_cpus; + unsigned int num_cpus; unsigned int bclk_khz; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/58916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ab0106c27a834d5d2ac1cb8023f4400a8ad91cd Gerrit-Change-Number: 58916 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/braswell: Make `num_cpus` unsigned
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58915 ) Change subject: soc/intel/braswell: Make `num_cpus` unsigned ...................................................................... soc/intel/braswell: Make `num_cpus` unsigned Change-Id: Iff6da3dc9c744a3dae3f4dd4ac37a91f348450a3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/braswell/include/soc/pattrs.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/58915/1 diff --git a/src/soc/intel/braswell/include/soc/pattrs.h b/src/soc/intel/braswell/include/soc/pattrs.h index 5cad6d0..3383589 100644 --- a/src/soc/intel/braswell/include/soc/pattrs.h +++ b/src/soc/intel/braswell/include/soc/pattrs.h @@ -29,7 +29,7 @@ int stepping; const void *microcode_patch; int address_bits; - int num_cpus; + unsigned int num_cpus; unsigned int bclk_khz; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/58915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff6da3dc9c744a3dae3f4dd4ac37a91f348450a3 Gerrit-Change-Number: 58915 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Refactor `get_threads_per_package()`
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Patrick Rudolph, Tim Chu. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58914 ) Change subject: soc/intel/xeon_sp: Refactor `get_threads_per_package()` ...................................................................... soc/intel/xeon_sp: Refactor `get_threads_per_package()` Reduce the visibility of the `get_threads_per_package()` function and retype its return value to `unsigned int`. Change-Id: Ie71730d9a89eb7c4bb82d09d140fbcec7a6fe5f3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/util.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/58914/1 diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 26bb3c3..213735a 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -9,7 +9,6 @@ void unlock_pam_regions(void); uint8_t get_stack_busno(const uint8_t stack); msr_t read_msr_ppin(void); -int get_threads_per_package(void); int get_platform_thread_count(void); const IIO_UDS *get_iio_uds(void); unsigned int soc_get_num_cpus(void); diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 579ebbc..4295704 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -74,7 +74,7 @@ return ppin; } -int get_threads_per_package(void) +static unsigned int get_threads_per_package(void) { unsigned int core_count, thread_count; cpu_read_topology(&core_count, &thread_count); -- To view, visit https://review.coreboot.org/c/coreboot/+/58914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71730d9a89eb7c4bb82d09d140fbcec7a6fe5f3 Gerrit-Change-Number: 58914 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton_ns: Refactor `detect_num_cpus_via_cpuid()`
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58913 ) Change subject: soc/intel/denverton_ns: Refactor `detect_num_cpus_via_cpuid()` ...................................................................... soc/intel/denverton_ns: Refactor `detect_num_cpus_via_cpuid()` Rewrite level type check and use unsigned types. In addition, also use unsigned types in the `get_cpu_count()` function. Change-Id: I63f236f0f94f9412ec03ae25781befe619cf7c1f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/denverton_ns/cpu.c 1 file changed, 10 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/58913/1 diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index c1bb4a9..96eb79a 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -162,21 +162,20 @@ *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } -static int detect_num_cpus_via_cpuid(void) +static unsigned int detect_num_cpus_via_cpuid(void) { - register int ecx = 0; - struct cpuid_result leaf_b; + unsigned int ecx = 0; while (1) { - leaf_b = cpuid_ext(0xb, ecx); + const struct cpuid_result leaf_b = cpuid_ext(0xb, ecx); /* Processor doesn't have hyperthreading so just determine the - * number of cores by from level type (ecx[15:8] == * 2). */ - if ((leaf_b.ecx & 0xff00) == 0x0200) - break; + number of cores from level type (ecx[15:8] == 2). */ + if ((leaf_b.ecx >> 8 & 0xff) == 2) + return leaf_b.ebx & 0xffff; + ecx++; } - return (leaf_b.ebx & 0xffff); } /* Assumes that FSP has already programmed the cores disabled register */ @@ -200,11 +199,11 @@ /* Find CPU topology */ int get_cpu_count(void) { - int num_cpus = detect_num_cpus_via_mch(); + unsigned int num_cpus = detect_num_cpus_via_mch(); - if (num_cpus <= 0 || num_cpus > CONFIG_MAX_CPUS) { + if (num_cpus == 0 || num_cpus > CONFIG_MAX_CPUS) { num_cpus = detect_num_cpus_via_cpuid(); - printk(BIOS_DEBUG, "Number of Cores (CPUID): %d.\n", num_cpus); + printk(BIOS_DEBUG, "Number of Cores (CPUID): %u.\n", num_cpus); } return num_cpus; } -- To view, visit https://review.coreboot.org/c/coreboot/+/58913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f236f0f94f9412ec03ae25781befe619cf7c1f Gerrit-Change-Number: 58913 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton_ns: Refactor `detect_num_cpus_via_mch()`
by Angel Pons (Code Review) 03 Nov '21

03 Nov '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58912 ) Change subject: soc/intel/denverton_ns: Refactor `detect_num_cpus_via_mch()` ...................................................................... soc/intel/denverton_ns: Refactor `detect_num_cpus_via_mch()` Use the `popcnt()` helper and use unsigned types. Change-Id: Iae6b16991fcf07c9ad67d2b737e490212b8deedd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/cpu.h 2 files changed, 9 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/58912/1 diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 44cb297..c1bb4a9 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -14,7 +14,7 @@ #include <device/device.h> #include <device/pci.h> #include <intelblocks/cpulib.h> - +#include <lib.h> #include <soc/msr.h> #include <soc/cpu.h> #include <soc/iomap.h> @@ -179,28 +179,19 @@ return (leaf_b.ebx & 0xffff); } -static int detect_num_cpus_via_mch(void) +/* Assumes that FSP has already programmed the cores disabled register */ +static unsigned int detect_num_cpus_via_mch(void) { - /* Assumes that FSP has already programmed the cores disabled register - */ - u32 core_exists_mask, active_cores_mask; - u32 core_disable_mask; - register int active_cores = 0, total_cores = 0; - register int counter = 0; - /* Get Masks for Total Existing SOC Cores and Core Disable Mask */ - core_exists_mask = MMIO32(DEFAULT_MCHBAR + MCH_BAR_CORE_EXISTS_MASK); - core_disable_mask = MMIO32(DEFAULT_MCHBAR + MCH_BAR_CORE_DISABLE_MASK); - active_cores_mask = (~core_disable_mask) & core_exists_mask; + const u32 core_exists_mask = MMIO32(DEFAULT_MCHBAR + MCH_BAR_CORE_EXISTS_MASK); + const u32 core_disable_mask = MMIO32(DEFAULT_MCHBAR + MCH_BAR_CORE_DISABLE_MASK); + const u32 active_cores_mask = ~core_disable_mask & core_exists_mask; /* Calculate Number of Active Cores */ - for (; counter < CONFIG_MAX_CPUS; - counter++, active_cores_mask >>= 1, core_exists_mask >>= 1) { - active_cores += (active_cores_mask & CORE_BIT_MSK); - total_cores += (core_exists_mask & CORE_BIT_MSK); - } + const unsigned int active_cores = popcnt(active_cores_mask); + const unsigned int total_cores = popcnt(core_exists_mask); - printk(BIOS_DEBUG, "Number of Active Cores: %d of %d total.\n", + printk(BIOS_DEBUG, "Number of Active Cores: %u of %u total.\n", active_cores, total_cores); return active_cores; diff --git a/src/soc/intel/denverton_ns/include/soc/cpu.h b/src/soc/intel/denverton_ns/include/soc/cpu.h index a714764..a8af626 100644 --- a/src/soc/intel/denverton_ns/include/soc/cpu.h +++ b/src/soc/intel/denverton_ns/include/soc/cpu.h @@ -11,7 +11,6 @@ #ifndef __ACPI__ #define MSR_CORE_THREAD_COUNT 0x35 -#define CORE_BIT_MSK 0x1 #define MCH_BAR_CORE_EXISTS_MASK 0x7164 #define MCH_BAR_CORE_DISABLE_MASK 0x7168 -- To view, visit https://review.coreboot.org/c/coreboot/+/58912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6b16991fcf07c9ad67d2b737e490212b8deedd Gerrit-Change-Number: 58912 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush/bootblock: add comment on selecting eSPI interface
by Raul Rangel (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58876 ) Change subject: mb/google/guybrush/bootblock: add comment on selecting eSPI interface ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb Gerrit-Change-Number: 58876 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Nov 2021 14:43:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/include/gpio: fix GPIO 106 native function names
by Raul Rangel (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58874 ) Change subject: soc/amd/cezanne/include/gpio: fix GPIO 106 native function names ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6 Gerrit-Change-Number: 58874 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Nov 2021 14:43:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guard
by Raul Rangel (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58864 ) Change subject: soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guard ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice2872b4a24032d3a65777795943602cd2595de7 Gerrit-Change-Number: 58864 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Nov 2021 14:42:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] ChromeOS: Add DECLARE_x_CROS_GPIOS()
by build bot (Jenkins) (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58899 ) Change subject: [RFC] ChromeOS: Add DECLARE_x_CROS_GPIOS() ...................................................................... Patch Set 3: (4 comments) File src/vendorcode/google/chromeos/chromeos.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132184): https://review.coreboot.org/c/coreboot/+/58899/comment/567c9bd3_0f4473da PS3, Line 110: #define DECLARE_CROS_GPIOS(x) \ Macros with flow control statements should be avoided Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132184): https://review.coreboot.org/c/coreboot/+/58899/comment/2004bbea_0d5a321c PS3, Line 111: const struct cros_gpio *variant_cros_gpios(size_t *num) \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132184): https://review.coreboot.org/c/coreboot/+/58899/comment/71ec52dc_10212d94 PS3, Line 117: #define DECLARE_WEAK_CROS_GPIOS(x) \ Macros with flow control statements should be avoided Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132184): https://review.coreboot.org/c/coreboot/+/58899/comment/7ce64469_f428a492 PS3, Line 118: const struct cros_gpio *__weak variant_cros_gpios(size_t *num) \ please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/58899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Gerrit-Change-Number: 58899 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Nov 2021 14:38:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ChromeOS: Add legacy mainboard_ec_running_ro()
by build bot (Jenkins) (Code Review) 03 Nov '21

03 Nov '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58896 ) Change subject: ChromeOS: Add legacy mainboard_ec_running_ro() ...................................................................... Patch Set 2: (1 comment) File src/vendorcode/google/chromeos/gnvs.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132181): https://review.coreboot.org/c/coreboot/+/58896/comment/1aa3d789_d6f85e77 PS2, Line 36: bool __weak mainboard_ec_running_ro() { return true; } Bad function definition - bool __weak mainboard_ec_running_ro() should probably be bool __weak mainboard_ec_running_ro(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/58896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Gerrit-Change-Number: 58896 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 Nov 2021 14:32:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021