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Change subject: src/lib: Support fallback option for fw_config
......................................................................
Patch Set 5:
(2 comments)
File src/lib/fw_config.c:
https://review.coreboot.org/c/coreboot/+/58833/comment/eec412bc_63e4d425
PS5, Line 31: fw_config_value = UNDEFINED_FW_CONFIG;
this line is now redundant
https://review.coreboot.org/c/coreboot/+/58833/comment/2662c0a3_3478e397
PS5, Line 43: fw_config_value = UNDEFINED_FW_CONFIG;
also redundant
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Change subject: mb/siemens/mc_ehl: Disable all P-States
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Patch Set 1: Code-Review+2
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Change subject: mb/siemens/mc_ehl: Disable C-States for CPU and package
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Patch Set 1: Code-Review+2
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Change subject: mb/siemens/mc_ehl2: Clean up devicetree
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/58887/comment/3fa14d87_1e6e580b
PS2, Line 100: [PchSerialIoIndexI2C0] = PchSerialIoPci,
: [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
: [PchSerialIoIndexI2C2] = PchSerialIoPci,
: [PchSerialIoIndexI2C3] = PchSerialIoPci,
: [PchSerialIoIndexI2C4] = PchSerialIoPci,
: [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
: [PchSerialIoIndexI2C6] = PchSerialIoDisabled,
: [PchSerialIoIndexI2C7] = PchSerialIoDisabled,
Once you are here you could adjust the SIO I2C enablement in FSP to match your usage. So since you have enabled I2C0-I2C5 in devicetree you should enable I2C0-5 here as well.
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Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
Patch Set 46:
(1 comment)
Patchset:
PS46:
> As I understand the situation now, using the PSE is optional and […]
Hi Nico, sorry for having not to reply to you on mailing list, just got back to coreboot work. I completely understood your reasoning and I agreed with you. I would love to make happy but currently my hands are tied, very unfortunately, because this PSE FW is managed by entirely other team. What make this even worse is that for EHL customers to use the PSE peripherals such as the 2 PSE ethernet ports, this PSE FW loading is a must. I have tried my best to convince the relevant team to open source the Zephyr OS codes (since it is Apache) or even just the documentation however there will be no further resources put in on this effort... (unless Intel's customer choose to open source it).
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Change subject: mb/google/brya/var/kano: Update GPIO table for speak and dmic
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Change subject: device/azalia_device.h: Rewrite verb macros
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Patch Set 1: Code-Review+2
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Change subject: drivers: Replace bad uses of `find_resource`
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Change subject: mdfwtool: Set soc name for Stoneyridge
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58555/comment/3c2c329b_7a471a4c
PS4, Line 7: md
amd
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