coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: mb/google/brya/var/felwinter: Correct typeC EC mux port
by EricR Lai (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58930 to look at the new patch set (#2). Change subject: mb/google/brya/var/felwinter: Correct typeC EC mux port ...................................................................... mb/google/brya/var/felwinter: Correct typeC EC mux port Type C port2 uses EC mux port0 as per schematics. BUG=b:204230406 TEST=No error message in depthahrge. update_port_state: port C2: get_usb_pd_mux_info failed Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/58930/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a Gerrit-Change-Number: 58930 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya/var/felwinter: Correct typeC EC mux port
by Paul Menzel (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58930 ) Change subject: mb/google/brya/var/felwinter: Correct typeC EC mux port ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58930/comment/f0d62b91_3a80bfa6 PS1, Line 9: Type C port2 is used EC mux port0. … as per schematics? https://review.coreboot.org/c/coreboot/+/58930/comment/c0c333d7_9e396bce PS1, Line 9: is used uses? -- To view, visit https://review.coreboot.org/c/coreboot/+/58930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a Gerrit-Change-Number: 58930 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 07:40:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/bugzzy: Enable Wifi SAR
by Henry Sun (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: shkim, Edward Doan, Karthik Ramasubramanian. Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58845 ) Change subject: mb/google/dedede/var/bugzzy: Enable Wifi SAR ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: LGTM, differ to Karthik to approve. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/58845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie967ef7fbc19886c631e634a0b0c3f2cf1e490af Gerrit-Change-Number: 58845 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: shkim <sh_.kim(a)samsung.com> Gerrit-Attention: Edward Doan <edoan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 07:37:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Documentation: Some notes about how to integrate FSP
by Paul Menzel (Code Review) 04 Nov '21

04 Nov '21

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58886 ) Change subject: Documentation: Some notes about how to integrate FSP ...................................................................... Patch Set 1: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58886/comment/c6084fba_769133b5 PS1, Line 7: Documentation: Some notes about how to integrate FSP Nit: Please add verb: Add some notes … File Documentation/soc/intel/fsp/index.md: https://review.coreboot.org/c/coreboot/+/58886/comment/541fd127_b62a3abb PS1, Line 8: has an effect on affects https://review.coreboot.org/c/coreboot/+/58886/comment/43ee9665_e64ad98e PS1, Line 11: * It should be possible to replace FSP based boot with a native : coreboot implementation for a given chipset without touching the : mainboard code. : * The devicetree configures coreboot and part of what coreboot does : with the information is setting some FSP UPDs. The devicetree isn't : supposed to directly configure FSP. Reflow for full textwidth? -- To view, visit https://review.coreboot.org/c/coreboot/+/58886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Gerrit-Change-Number: 58886 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 07:34:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/metaknight: Probe and enable amplifier operation...
by David Wu (Code Review) 04 Nov '21

04 Nov '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58931 ) Change subject: mb/google/dedede/var/metaknight: Probe and enable amplifier operation mode ...................................................................... mb/google/dedede/var/metaknight: Probe and enable amplifier operation mode Probe the fw_config for RT1015 speaker amplifier operation mode and enable it accordingly in the device tree. BUG=none BRANCH=dedede TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I2de1487b7f4767e9ba6432174c39feeb25f9534c --- M src/mainboard/google/dedede/variants/metaknight/overridetree.cb 1 file changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/58931/1 diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 725750b..bb4762f 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -243,15 +243,28 @@ register "hid" = ""10EC1015"" register "desc" = ""Realtek SPK AMP L"" register "uid" = "0" - device i2c 28 on end + device i2c 28 on + probe AUDIO_AMP UNPROVISIONED + probe AUDIO_AMP RT1015_I2C + end end chip drivers/i2c/generic register "hid" = ""10EC1015"" register "desc" = ""Realtek SPK AMP R"" register "uid" = "1" - device i2c 29 on end + device i2c 29 on + probe AUDIO_AMP UNPROVISIONED + probe AUDIO_AMP RT1015_I2C + end end end - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on + chip drivers/generic/alc1015 + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on + probe AUDIO_AMP RT1015P_AUTO + end + end + end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/58931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2de1487b7f4767e9ba6432174c39feeb25f9534c Gerrit-Change-Number: 58931 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Reka Norman (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58679 ) Change subject: util/spd_tools: Add LP5 support for ADL ...................................................................... Patch Set 11: (1 comment) File util/spd_tools/src/spd_gen/lp5.go: https://review.coreboot.org/c/coreboot/+/58679/comment/a44eebfb_e0702002 PS5, Line 18: DensityPerDieGb int > I'm not familiar with this. I'll look into it. I assume you're talking about MEM_CH_SEL? E.g. https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… My understanding of this still isn't great, so I could be completely wrong. But I think these are two different uses of the term channel: 1. What we're talking about here is the channels per die. This is a detail of the memory part's internal structure, i.e. which of the part's x8/x16 IO channels are connected to which dies internally. 2. MEM_CH_SEL is talking about the SoC's memory channels. E.g. ADL-P has 2 x64 channels A and B, and I think setting MEM_CH_SEL means that only one of these channels is used. -- To view, visit https://review.coreboot.org/c/coreboot/+/58679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Gerrit-Change-Number: 58679 Gerrit-PatchSet: 11 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 05:32:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: treewide: Replace bad uses of `find_resource`
by Lance Zhao (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Angel Pons. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58910 ) Change subject: treewide: Replace bad uses of `find_resource` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I329efcb42a444b097794fde4f40acf5ececaea8c Gerrit-Change-Number: 58910 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 05:26:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/guybrush/bootblock: add comment on selecting eSPI interface
by Felix Held (Code Review) 04 Nov '21

04 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58876 ) Change subject: mb/google/guybrush/bootblock: add comment on selecting eSPI interface ...................................................................... mb/google/guybrush/bootblock: add comment on selecting eSPI interface Setting the PM_ESPI_CS_USE_DATA2 bit in PM_SPI_PAD_PU_PD results in the eSPI transactions being sent via the SPI2 pins instead of the SPI1 pins. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58876 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/guybrush/bootblock.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 83ac43a..187b2ef 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -63,6 +63,7 @@ /* Early eSPI interface configuration */ + /* Use SPI2 pins for eSPI */ dword = pm_read32(PM_SPI_PAD_PU_PD); dword |= PM_ESPI_CS_USE_DATA2; pm_write32(PM_SPI_PAD_PU_PD, dword); -- To view, visit https://review.coreboot.org/c/coreboot/+/58876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb Gerrit-Change-Number: 58876 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya/var/felwinter: Correct typeC EC mux port
by EricR Lai (Code Review) 04 Nov '21

04 Nov '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58930 ) Change subject: mb/google/brya/var/felwinter: Correct typeC EC mux port ...................................................................... mb/google/brya/var/felwinter: Correct typeC EC mux port Type C port2 is used EC mux port0. BUG=b:204230406 TEST=No error message in depthahrge. update_port_state: port C2: get_usb_pd_mux_info failed Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/58930/1 diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 0fa2e61..6921b70 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -126,7 +126,7 @@ #TBD, felwinter remove typeC port0 chip ec/google/chromeec use conn1 as mux_conn[1] - use conn2 as mux_conn[2] + use conn2 as mux_conn[0] device pnp 0c09.0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/58930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a Gerrit-Change-Number: 58930 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/cezanne/include/gpio: fix GPIO 106 native function names
by Felix Held (Code Review) 04 Nov '21

04 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58874 ) Change subject: soc/amd/cezanne/include/gpio: fix GPIO 106 native function names ...................................................................... soc/amd/cezanne/include/gpio: fix GPIO 106 native function names The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed that the native function names don't have the EMMC_ prefix. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/soc/amd/cezanne/include/soc/gpio.h 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 89594fa..66b40be 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -117,7 +117,7 @@ /* ESPI1_DATA1 */ PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), /* ESPI1_DATA2 */ - PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), + PAD_NF(GPIO_106, SPI2_WP_L_ESPI2_D2, PULL_NONE), /* ESPI1_DATA3 */ PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* ESPI_ALERT_L */ @@ -217,7 +217,7 @@ /* ESPI1_DATA1 */ PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), /* ESPI1_DATA2 */ - PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), + PAD_NF(GPIO_106, SPI2_WP_L_ESPI2_D2, PULL_NONE), /* ESPI1_DATA3 */ PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* ESPI_ALERT_L */ diff --git a/src/soc/amd/cezanne/include/soc/gpio.h b/src/soc/amd/cezanne/include/soc/gpio.h index 904c3fc..d12d667 100644 --- a/src/soc/amd/cezanne/include/soc/gpio.h +++ b/src/soc/amd/cezanne/include/soc/gpio.h @@ -235,8 +235,8 @@ #define GPIO_105_IOMUX_SD0_DATA1 2 #define GPIO_105_IOMUX_GPIOxx 3 #define GPIO_106_IOMUX_LAD2 0 -#define GPIO_106_IOMUX_EMMC_SPI2_WP_L_ESPI2_D2 1 -#define GPIO_106_IOMUX_EMMC_SD0_DATA2 2 +#define GPIO_106_IOMUX_SPI2_WP_L_ESPI2_D2 1 +#define GPIO_106_IOMUX_SD0_DATA2 2 #define GPIO_106_IOMUX_GPIOxx 3 #define GPIO_107_IOMUX_LAD3 0 #define GPIO_107_IOMUX_SPI2_HOLD_L_ESPI2_D3 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6 Gerrit-Change-Number: 58874 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021