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Change subject: mb/google/dedede/var/bugzzy: Update charger performance control table
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58840/comment/99fec89c_964a009c
PS1, Line 9: Update charger performance control table of DPTF for bugzzy.
Please amend the message, and document where you got the values from.
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Change subject: spd: Add new LP5 parts and generate SPDs
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58929/comment/2e7a07dc_0fce977b
PS2, Line 12: MT62F512M32D2DR-031 WT:B
: MT62F1G32D4DR-031 WT:B
: H9JCNNNCP3MLYR-N6E
Please add the vendors.
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Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58640/comment/80b3681c_ca1081db
PS2, Line 10:
> I have added these comments for each module.
Thank you for addressing my concers.
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Change subject: mb/google/brya/var/felwinter: Correct typeC EC mux port
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58930/comment/73b58132_67eedb07
PS1, Line 9: is used
> uses?
Done
https://review.coreboot.org/c/coreboot/+/58930/comment/f11ce6f3_0594cfcc
PS1, Line 9: Type C port2 is used EC mux port0.
> … as per schematics?
Done
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58930
to look at the new patch set (#2).
Change subject: mb/google/brya/var/felwinter: Correct typeC EC mux port
......................................................................
mb/google/brya/var/felwinter: Correct typeC EC mux port
Type C port2 uses EC mux port0 as per schematics.
BUG=b:204230406
TEST=No error message in depthahrge.
update_port_state: port C2: get_usb_pd_mux_info failed
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a
---
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/58930/2
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Change subject: mb/google/brya/var/felwinter: Correct typeC EC mux port
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58930/comment/f0d62b91_3a80bfa6
PS1, Line 9: Type C port2 is used EC mux port0.
… as per schematics?
https://review.coreboot.org/c/coreboot/+/58930/comment/c0c333d7_9e396bce
PS1, Line 9: is used
uses?
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Change subject: mb/google/dedede/var/bugzzy: Enable Wifi SAR
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
LGTM, differ to Karthik to approve. Thanks!
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58886 )
Change subject: Documentation: Some notes about how to integrate FSP
......................................................................
Patch Set 1: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58886/comment/c6084fba_769133b5
PS1, Line 7: Documentation: Some notes about how to integrate FSP
Nit: Please add verb: Add some notes …
File Documentation/soc/intel/fsp/index.md:
https://review.coreboot.org/c/coreboot/+/58886/comment/541fd127_b62a3abb
PS1, Line 8: has an effect on
affects
https://review.coreboot.org/c/coreboot/+/58886/comment/43ee9665_e64ad98e
PS1, Line 11: * It should be possible to replace FSP based boot with a native
: coreboot implementation for a given chipset without touching the
: mainboard code.
: * The devicetree configures coreboot and part of what coreboot does
: with the information is setting some FSP UPDs. The devicetree isn't
: supposed to directly configure FSP.
Reflow for full textwidth?
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Change subject: util/spd_tools: Add LP5 support for ADL
......................................................................
Patch Set 11:
(1 comment)
File util/spd_tools/src/spd_gen/lp5.go:
https://review.coreboot.org/c/coreboot/+/58679/comment/a44eebfb_e0702002
PS5, Line 18: DensityPerDieGb int
> I'm not familiar with this. I'll look into it.
I assume you're talking about MEM_CH_SEL? E.g. https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr…
My understanding of this still isn't great, so I could be completely wrong. But I think these are two different uses of the term channel:
1. What we're talking about here is the channels per die. This is a detail of the memory part's internal structure, i.e. which of the part's x8/x16 IO channels are connected to which dies internally.
2. MEM_CH_SEL is talking about the SoC's memory channels. E.g. ADL-P has 2 x64 channels A and B, and I think setting MEM_CH_SEL means that only one of these channels is used.
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