coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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5770 discussions

Change in coreboot[master]: mb/system76/oryp8: Add System76 Oryx Pro 8

by Tim Crawford (Code Review)

Attention is currently required from: Jeremy Soller. Hello build bot (Jenkins), Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57652 to look at the new patch set (#5). Change subject: mb/system76/oryp8: Add System76 Oryx Pro 8 ...................................................................... mb/system76/oryp8: Add System76 Oryx Pro 8 https://tech-docs.system76.com/models/oryp8/README.html Tested with TianoCore (UeifPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone & microphone jack - Combined 3.5mm microphone & S/PDIF jack* - S3 suspend/resume - Booting to Pop!_OS Linux 21.10 and Windows 10 20H2 - Flashing with flashrom Not working: - Discrete/Hybrid graphics Not tested: - Thunderbolt functionality - S/PDIF output Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/oryp8.md A src/mainboard/system76/oryp8/Kconfig A src/mainboard/system76/oryp8/Kconfig.name A src/mainboard/system76/oryp8/Makefile.inc A src/mainboard/system76/oryp8/acpi/mainboard.asl A src/mainboard/system76/oryp8/acpi/sleep.asl A src/mainboard/system76/oryp8/board_info.txt A src/mainboard/system76/oryp8/bootblock.c A src/mainboard/system76/oryp8/cmos.default A src/mainboard/system76/oryp8/cmos.layout A src/mainboard/system76/oryp8/data.vbt A src/mainboard/system76/oryp8/devicetree.cb A src/mainboard/system76/oryp8/dsdt.asl A src/mainboard/system76/oryp8/gpio.c A src/mainboard/system76/oryp8/gpio_early.c A src/mainboard/system76/oryp8/hda_verb.c A src/mainboard/system76/oryp8/include/mainboard/gpio.h A src/mainboard/system76/oryp8/ramstage.c A src/mainboard/system76/oryp8/romstage.c A src/mainboard/system76/oryp8/tas5825m.c 21 files changed, 2,696 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/57652/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/57652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb Gerrit-Change-Number: 57652 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newpatchset

6 months, 3 weeks

Change in coreboot[master]: soc/intel/alderlake: enable gpio locking

by Nick Vaccaro (Code Review)

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58352 ) Change subject: soc/intel/alderlake: enable gpio locking ...................................................................... Patch Set 4: (2 comments) File src/soc/intel/alderlake/gpio.c: https://review.coreboot.org/c/coreboot/+/58352/comment/264cef26_a81c9597 PS1, Line 251: #if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS) > I think you can make it work without any #ifs whatsoever and no weak functions either. […] The way it works now, either the MB or the SoC can define the Kconfig without requiring the other one to be implemented. If we remove weak functions, we'll have to implement both SoC and MB at the same time. Or we say that SoC implementation must be first and they own the Kconfig and must implement a weak mb_gpio_lock_config() when they add their code that enables SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS. Preference? Once we finish hashing this out and agree that the end-resulting code is the right approach, I'll implement this for TGL. https://review.coreboot.org/c/coreboot/+/58352/comment/c4d6837e_8685283f PS1, Line 250: : #if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS) > I don't think this is required Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Gerrit-Change-Number: 58352 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 01 Nov 2021 20:32:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

6 months, 3 weeks

Change in edk2[coreboot-stable202108]: run-jenkins-tests: build in verbose mode

by Matt DeVillier (Code Review)

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/edk2/+/58797 ) Change subject: run-jenkins-tests: build in verbose mode ...................................................................... run-jenkins-tests: build in verbose mode Diagnosing build failures when '-q' is used is very difficult, so drop it to get verbose build output info. Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Change-Id: I3847da7039d073c1f8ba87cc0ea56fdb3bedc3da --- M run-jenkins-tests.sh 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/edk2 refs/changes/97/58797/1 diff --git a/run-jenkins-tests.sh b/run-jenkins-tests.sh index 43b0f43..dfde53b 100755 --- a/run-jenkins-tests.sh +++ b/run-jenkins-tests.sh @@ -23,10 +23,10 @@ make -C BaseTools/Source/C -j "${CPUS}" # Make sure that whatever we do, we don't break upstream use cases -build -q -t COREBOOT -j "${CPUS}" -a X64 -p OvmfPkg/OvmfPkgX64.dsc -build -q -t COREBOOT -j "${CPUS}" -a IA32 -p OvmfPkg/OvmfPkgIa32.dsc -build -q -t COREBOOT -j "${CPUS}" -a IA32 -a X64 -p OvmfPkg/OvmfPkgIa32X64.dsc +build -t COREBOOT -j "${CPUS}" -a X64 -p OvmfPkg/OvmfPkgX64.dsc +build -t COREBOOT -j "${CPUS}" -a IA32 -p OvmfPkg/OvmfPkgIa32.dsc +build -t COREBOOT -j "${CPUS}" -a IA32 -a X64 -p OvmfPkg/OvmfPkgIa32X64.dsc # Test coreboot payload configs -build -q -t COREBOOT -j "${CPUS}" -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -b DEBUG -D BOOTLOADER=COREBOOT -D PS2_KEYBOARD_ENABLE -build -q -t COREBOOT -j "${CPUS}" -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -b RELEASE -D BOOTLOADER=COREBOOT -D PS2_KEYBOARD_ENABLE +build -t COREBOOT -j "${CPUS}" -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -b DEBUG -D BOOTLOADER=COREBOOT -D PS2_KEYBOARD_ENABLE +build -t COREBOOT -j "${CPUS}" -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -b RELEASE -D BOOTLOADER=COREBOOT -D PS2_KEYBOARD_ENABLE -- To view, visit https://review.coreboot.org/c/edk2/+/58797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: edk2 Gerrit-Branch: coreboot-stable202108 Gerrit-Change-Id: I3847da7039d073c1f8ba87cc0ea56fdb3bedc3da Gerrit-Change-Number: 58797 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

6 months, 3 weeks

Change in coreboot[master]: soc/intel/common: add generic gpio lock mechanism

by Nick Vaccaro (Code Review)

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58351 ) Change subject: soc/intel/common: add generic gpio lock mechanism ...................................................................... Patch Set 4: (2 comments) File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/58351/comment/4610ef3a_4ac422cf PS3, Line 473: > Nit: Extra line can be removed. Done https://review.coreboot.org/c/coreboot/+/58351/comment/bb925990_7912a13a PS3, Line 561: int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action action) > Can the function body be replaced as: […] It won't be quite as efficient as calling gpio_lock_pad directly, but it does avoid duplicated logic and save some source code space. Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/58351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Gerrit-Change-Number: 58351 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 01 Nov 2021 20:24:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

6 months, 3 weeks

Change in coreboot[master]: soc/intel/common: add generic gpio lock mechanism

by Nick Vaccaro (Code Review)

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58351 to look at the new patch set (#4). Change subject: soc/intel/common: add generic gpio lock mechanism ...................................................................... soc/intel/common: add generic gpio lock mechanism For added security, there are some gpios that an SoC will want to lock once initially configured, such as gpios attached to non-host (x86) controllers, so that they can't be recofigured at a later point in time by rogue code. Likewise, a mainboard may have some gpios connected to secure busses and/or devices that they want to protect from being changed post initial configuration. This change adds a generic gpio locking mechanism that allows the SoC to export a list of GPIOs to be locked down and allows the mainboard to export a list of GPIOs that it wants locked down once initialization is complete. Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to enable this feature. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify brya0 boots successfully to kernel. Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/common/block/smm/smihandler.c 4 files changed, 162 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/58351/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Gerrit-Change-Number: 58351 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

6 months, 3 weeks

Change in coreboot[master]: mb/system76/*: CMOS: Drop power_on_after_fail option

by Jeremy Soller (Code Review)

Attention is currently required from: Tim Crawford. Jeremy Soller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58673 ) Change subject: mb/system76/*: CMOS: Drop power_on_after_fail option ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1857e52f838337048f79f8ca5c12d669cae321a Gerrit-Change-Number: 58673 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Comment-Date: Mon, 01 Nov 2021 20:24:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

6 months, 3 weeks

Change in coreboot[master]: mb/system76/gaze16: Add System76 Gazelle 16

by Tim Crawford (Code Review)

Hello build bot (Jenkins), Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56956 to look at the new patch set (#15). Change subject: mb/system76/gaze16: Add System76 Gazelle 16 ...................................................................... mb/system76/gaze16: Add System76 Gazelle 16 https://tech-docs.system76.com/models/gaze16/README.html The gaze16 comes in 3 variants due to differences in the discrete GPU and network controller used. - NVIDIA RTX 3050, using Realtek Ethernet controller - NVIDIA RTX 3060, using Realtek Ethernet controller - NVIDIA RTX 3060, using onboard Intel I219-V Ethernet controller Tested on the 3050 variant. Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe SSD - M.2 SATA SSD - 2.5" SSD - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio* - 3.5mm microphone input* - S3 suspend/resume - Booting to Pop!_OS Linux 21.04 and Windows 10 20H2 - Flashing with flashrom Not working: - Discrete/Hybrid graphics - Mini DisplayPort output (requires NVIDIA GPU) - 3.5mm audio input/output detection on Windows Change-Id: Ifb90f9b73a10abf53a21738e2c466d539df9a37c Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/gaze16.md A src/mainboard/system76/gaze16/Kconfig A src/mainboard/system76/gaze16/Kconfig.name A src/mainboard/system76/gaze16/Makefile.inc A src/mainboard/system76/gaze16/acpi/mainboard.asl A src/mainboard/system76/gaze16/acpi/sleep.asl A src/mainboard/system76/gaze16/board_info.txt A src/mainboard/system76/gaze16/bootblock.c A src/mainboard/system76/gaze16/cmos.default A src/mainboard/system76/gaze16/cmos.layout A src/mainboard/system76/gaze16/devicetree.cb A src/mainboard/system76/gaze16/dsdt.asl A src/mainboard/system76/gaze16/ramstage.c A src/mainboard/system76/gaze16/romstage.c A src/mainboard/system76/gaze16/variant.h A src/mainboard/system76/gaze16/variants/3050/data.vbt A src/mainboard/system76/gaze16/variants/3050/hda_verb.c A src/mainboard/system76/gaze16/variants/3050/include/variant/gpio.h A src/mainboard/system76/gaze16/variants/3050/overridetree.cb A src/mainboard/system76/gaze16/variants/3050/ramstage.c A src/mainboard/system76/gaze16/variants/3050/romstage.c A src/mainboard/system76/gaze16/variants/3060/data.vbt A src/mainboard/system76/gaze16/variants/3060/hda_verb.c A src/mainboard/system76/gaze16/variants/3060/include/variant/gpio.h A src/mainboard/system76/gaze16/variants/3060/overridetree.cb A src/mainboard/system76/gaze16/variants/3060/ramstage.c A src/mainboard/system76/gaze16/variants/3060/romstage.c 28 files changed, 1,365 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/56956/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/56956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb90f9b73a10abf53a21738e2c466d539df9a37c Gerrit-Change-Number: 56956 Gerrit-PatchSet: 15 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

6 months, 3 weeks

Change in coreboot[master]: SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries

by Tim Wawrzynczak (Code Review)

Attention is currently required from: Nico Huber, Martin Roth, Furquan Shaikh, Paul Menzel, Angel Pons, Arthur Heymans, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57370 ) Change subject: SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries ...................................................................... Patch Set 6: (1 comment) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/57370/comment/fc86ec2c_728bf75a PS6, Line 1186: = {} nit: is this necessary? a static should still get zeroed out? -- To view, visit https://review.coreboot.org/c/coreboot/+/57370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b Gerrit-Change-Number: 57370 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Nov 2021 19:46:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

6 months, 3 weeks

Change in coreboot[master]: include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDs

by Jason Glenesk (Code Review)

Attention is currently required from: Raul Rangel, Marshall Dawson, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58696 ) Change subject: include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDs ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede Gerrit-Change-Number: 58696 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 19:45:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

6 months, 3 weeks

Change in coreboot[master]: SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries

by Tim Wawrzynczak (Code Review)

Attention is currently required from: Nico Huber, Martin Roth, Furquan Shaikh, Paul Menzel, Angel Pons, Arthur Heymans, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57370 ) Change subject: SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57370/comment/ae8bb045_a2869cf1 PS4, Line 35: Although the preprocessor usage isn't particularly elegant, adjusting : the devicetree syntax and/or grammar depending on a Kconfig option is : probably even worse. > A linked list of properties, similar to the linked list of PCIe capabilities? Sounds good. Agreed they are necessary with things as they stand right now, it's just not a great solution. A linked-list is a neat idea, would love to see what you have up your sleeves 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/57370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b Gerrit-Change-Number: 57370 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Nov 2021 19:44:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021