coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guard
by Felix Held (Code Review) 04 Nov '21

04 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58864 ) Change subject: soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guard ...................................................................... soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guard This makes this header file consistent with the rest. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ice2872b4a24032d3a65777795943602cd2595de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58864 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/include/soc/cppc.h 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/cppc.h b/src/soc/amd/cezanne/include/soc/cppc.h index e2f4daa..41f6687 100644 --- a/src/soc/amd/cezanne/include/soc/cppc.h +++ b/src/soc/amd/cezanne/include/soc/cppc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _CPU_AMD_COMMON_H -#define _CPU_AMD_COMMON_H +#ifndef AMD_CEZANNE_CPPC_H +#define AMD_CEZANNE_CPPC_H #include <types.h> #include <acpi/acpigen.h> @@ -10,4 +10,4 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version); void generate_cppc_entries(unsigned int core_id); -#endif +#endif /* AMD_CEZANNE_CPPC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice2872b4a24032d3a65777795943602cd2595de7 Gerrit-Change-Number: 58864 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/corsola: Add NOR-Flash support
by Rex-BC Chen (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Hung-Te Lin, Felix Held. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58838 ) Change subject: mb/google/corsola: Add NOR-Flash support ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/corsola/bootblock.c: PS3: > There is two sets of GPIO for SPINOR on 8186. […] I will move these to soc first. -- To view, visit https://review.coreboot.org/c/coreboot/+/58838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee3dd336632b0cf998f5f7c1d118e01e8270e815 Gerrit-Change-Number: 58838 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Nov 2021 03:12:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: Add NOR-Flash support
by Rex-BC Chen (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Hung-Te Lin, Felix Held. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58838 ) Change subject: mb/google/corsola: Add NOR-Flash support ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/mainboard/google/corsola/bootblock.c: PS3: > some of the gpio struct definitions and handling code in here looks to me that it should probably be […] There is two sets of GPIO for SPINOR on 8186. It is determined by how boards use these GPIOs. -- To view, visit https://review.coreboot.org/c/coreboot/+/58838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee3dd336632b0cf998f5f7c1d118e01e8270e815 Gerrit-Change-Number: 58838 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Nov 2021 02:49:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: spd: Add new LP5 parts and generate SPDs
by Reka Norman (Code Review) 04 Nov '21

04 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58929 to look at the new patch set (#2). Change subject: spd: Add new LP5 parts and generate SPDs ...................................................................... spd: Add new LP5 parts and generate SPDs Add the following parts which will be used by the brya variant Vell. Add the parts to memory_parts.json and generate the SPDs using spd_gen. MT62F512M32D2DR-031 WT:B MT62F1G32D4DR-031 WT:B H9JCNNNCP3MLYR-N6E Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: Ifbcadfb78281b2b78a61a9b61180c421748193a0 Signed-off-by: Reka Norman <rekanorman(a)google.com> --- M spd/lp5/memory_parts.json M spd/lp5/set-0/parts_spd_manifest.generated.txt A spd/lp5/set-0/spd-1.hex A spd/lp5/set-0/spd-2.hex 4 files changed, 99 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/58929/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbcadfb78281b2b78a61a9b61180c421748193a0 Gerrit-Change-Number: 58929 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/kukui: Add new config 'pico6' in coreboot
by Chen-Tsung Hsieh (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: David Wu, Lucas Chen, Shou-Chieh Hsu. Chen-Tsung Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58885 ) Change subject: mb/google/kukui: Add new config 'pico6' in coreboot ...................................................................... Patch Set 2: Code-Review-1 (1 comment) Patchset: PS2: We don't really need this patch to create Pico6 FW. According to https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/…, the plan is reuse pico firmware for Pico6 and take pico6 as a sku e of Pcio. -- To view, visit https://review.coreboot.org/c/coreboot/+/58885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9413146913a38ed6a016b6b23ebd6c23040f4469 Gerrit-Change-Number: 58885 Gerrit-PatchSet: 2 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 02:28:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/galtic: update Wifi SAR for convertibles
by Frank Chu (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Henry Sun, Karthik Ramasubramanian. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58734 ) Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Gerrit-Change-Number: 58734 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 02:28:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: Add NOR-Flash support
by Felix Held (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58838 ) Change subject: mb/google/corsola: Add NOR-Flash support ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/corsola/bootblock.c: PS3: some of the gpio struct definitions and handling code in here looks to me that it should probably be moved to the soc code, since setting up the spi gpio pads won't be the only place where gpio pads need to be set up. if you prefer to do that at a later point in time, feel free to ack this one -- To view, visit https://review.coreboot.org/c/coreboot/+/58838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee3dd336632b0cf998f5f7c1d118e01e8270e815 Gerrit-Change-Number: 58838 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 02:07:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/*: Enable HECI device
by Felix Held (Code Review) 04 Nov '21

04 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58670 ) Change subject: mb/system76/*: Enable HECI device ...................................................................... mb/system76/*: Enable HECI device The HECI device needs to be enabled to send the commands to have the CSME change between Soft Temporary Disable mode and Normal mode. Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58670 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/darp7/devicetree.cb M src/mainboard/system76/galp5/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/lemp10/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb 9 files changed, 6 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 00cc3b8..4f16bbd 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -98,7 +98,7 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index 232d36c..da86024 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -98,7 +98,7 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index 1397097..8c16d2a 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -245,7 +245,6 @@ register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" end device ref heci1 on - # TODO Disable ME and HECI register "HeciEnabled" = "1" end device ref uart2 on diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index cf3a75e..b0fa524 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -256,7 +256,6 @@ register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" end device ref heci1 on - # TODO Disable ME and HECI register "HeciEnabled" = "1" end device ref uart2 on diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index cf0965b..c02a6ec 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -95,7 +95,7 @@ device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index 1362b3d..5c702b9 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -226,7 +226,6 @@ register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" end device ref heci1 on - # TODO Disable ME and HECI register "HeciEnabled" = "1" end device ref uart2 on diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 5648ca8..00d3708 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -102,7 +102,7 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index b55cbbe..bb75616 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -108,7 +108,7 @@ device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 8fc274b..85b5d26 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -110,7 +110,7 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection -- To view, visit https://review.coreboot.org/c/coreboot/+/58670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0 Gerrit-Change-Number: 58670 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8186: Add NOR-Flash support
by Felix Held (Code Review) 04 Nov '21

04 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58837 ) Change subject: soc/mediatek/mt8186: Add NOR-Flash support ...................................................................... soc/mediatek/mt8186: Add NOR-Flash support Add NOR-Flash drivers to pass verification of flash at verstage. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: If51d765e1fd4895f97898710ec6fa1374e1048fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58837 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8186/Kconfig M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/include/soc/symbols.h M src/soc/mediatek/mt8186/spi.c 4 files changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig index 9fa391a..1821fa9 100644 --- a/src/soc/mediatek/mt8186/Kconfig +++ b/src/soc/mediatek/mt8186/Kconfig @@ -16,4 +16,11 @@ select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE +config FLASH_DUAL_READ + bool + default y + help + When this option is enabled, the flash controller provides the ability + to dual read mode. + endif diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 76dac4b..366c706 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8186),y) bootblock-y += bootblock.c +bootblock-y += ../common/flash_controller.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c bootblock-$(CONFIG_SPI_FLASH) += spi.c @@ -8,6 +9,7 @@ bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c wdt.c +verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += spi.c verstage-y += ../common/timer.c @@ -16,6 +18,7 @@ romstage-y += ../common/cbmem.c romstage-y += emi.c +romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += ../common/timer.c @@ -23,6 +26,7 @@ romstage-y += ../common/wdt.c wdt.c ramstage-y += emi.c +ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += soc.c diff --git a/src/soc/mediatek/mt8186/include/soc/symbols.h b/src/soc/mediatek/mt8186/include/soc/symbols.h new file mode 100644 index 0000000..7610224 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/symbols.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MEDIATEK_MT8186_SYMBOLS_H_ +#define _SOC_MEDIATEK_MT8186_SYMBOLS_H_ + +#include <symbols.h> + +DECLARE_REGION(dram_dma) + +#endif /* _SOC_MEDIATEK_MT8186_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c index 9504925..e72b50f 100644 --- a/src/soc/mediatek/mt8186/spi.c +++ b/src/soc/mediatek/mt8186/spi.c @@ -7,15 +7,19 @@ #include <device/mmio.h> #include <soc/addressmap.h> +#include <soc/flash_controller_common.h> #include <soc/spi.h> static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, + .flash_probe = mtk_spi_flash_probe, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &spi_flash_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, }; 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If51d765e1fd4895f97898710ec6fa1374e1048fb Gerrit-Change-Number: 58837 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8186: Add NOR-Flash support
by Felix Held (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58837 ) Change subject: soc/mediatek/mt8186: Add NOR-Flash support ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8186/Kconfig: https://review.coreboot.org/c/coreboot/+/58837/comment/40a98af1_dce6bb2b PS3, Line 19: config FLASH_DUAL_READ i guess this is about the dual io read mode? if that's the case, maybe rename this to FLASH_DUAL_IO_READ, since that makes it at least for me clearer what this is about. or instead change it the help text to "dual IO read mode"? it's the same on all other existing mediatek socs, so i'll submit this patch as it is right now, but might be good to address this for all mediatek socs in a follow-up commit -- To view, visit https://review.coreboot.org/c/coreboot/+/58837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If51d765e1fd4895f97898710ec6fa1374e1048fb Gerrit-Change-Number: 58837 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 01:56:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021