Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: spd: Add new LP5 parts and generate SPDs
......................................................................
spd: Add new LP5 parts and generate SPDs
Add the following parts which will be used by the brya variant Vell. Add
the parts to memory_parts.json and generate the SPDs using spd_gen.
MT62F512M32D2DR-031 WT:B
MT62F1G32D4DR-031 WT:B
H9JCNNNCP3MLYR-N6E
Generated using:
util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
BUG=b:204284866
TEST=None
Change-Id: Ifbcadfb78281b2b78a61a9b61180c421748193a0
Signed-off-by: Reka Norman <rekanorman(a)google.com>
---
M spd/lp5/memory_parts.json
M spd/lp5/set-0/parts_spd_manifest.generated.txt
A spd/lp5/set-0/spd-1.hex
A spd/lp5/set-0/spd-2.hex
4 files changed, 99 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/58929/2
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Gerrit-Change-Number: 58929
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Change subject: mb/google/kukui: Add new config 'pico6' in coreboot
......................................................................
Patch Set 2: Code-Review-1
(1 comment)
Patchset:
PS2:
We don't really need this patch to create Pico6 FW. According to https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/…, the plan is reuse pico firmware for Pico6 and take pico6 as a sku e of Pcio.
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Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles
......................................................................
Patch Set 5: Code-Review+1
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Change subject: mb/google/corsola: Add NOR-Flash support
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/corsola/bootblock.c:
PS3:
some of the gpio struct definitions and handling code in here looks to me that it should probably be moved to the soc code, since setting up the spi gpio pads won't be the only place where gpio pads need to be set up. if you prefer to do that at a later point in time, feel free to ack this one
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58670 )
Change subject: mb/system76/*: Enable HECI device
......................................................................
mb/system76/*: Enable HECI device
The HECI device needs to be enabled to send the commands to have the
CSME change between Soft Temporary Disable mode and Normal mode.
Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58670
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jeremy Soller <jeremy(a)system76.com>
---
M src/mainboard/system76/addw1/devicetree.cb
M src/mainboard/system76/cml-u/devicetree.cb
M src/mainboard/system76/darp7/devicetree.cb
M src/mainboard/system76/galp5/devicetree.cb
M src/mainboard/system76/gaze15/devicetree.cb
M src/mainboard/system76/lemp10/devicetree.cb
M src/mainboard/system76/lemp9/devicetree.cb
M src/mainboard/system76/oryp5/devicetree.cb
M src/mainboard/system76/oryp6/devicetree.cb
9 files changed, 6 insertions(+), 9 deletions(-)
Approvals:
build bot (Jenkins): Verified
Jeremy Soller: Looks good to me, approved
diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb
index 00cc3b8..4f16bbd 100644
--- a/src/mainboard/system76/addw1/devicetree.cb
+++ b/src/mainboard/system76/addw1/devicetree.cb
@@ -98,7 +98,7 @@
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb
index 232d36c..da86024 100644
--- a/src/mainboard/system76/cml-u/devicetree.cb
+++ b/src/mainboard/system76/cml-u/devicetree.cb
@@ -98,7 +98,7 @@
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb
index 1397097..8c16d2a 100644
--- a/src/mainboard/system76/darp7/devicetree.cb
+++ b/src/mainboard/system76/darp7/devicetree.cb
@@ -245,7 +245,6 @@
register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
end
device ref heci1 on
- # TODO Disable ME and HECI
register "HeciEnabled" = "1"
end
device ref uart2 on
diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb
index cf3a75e..b0fa524 100644
--- a/src/mainboard/system76/galp5/devicetree.cb
+++ b/src/mainboard/system76/galp5/devicetree.cb
@@ -256,7 +256,6 @@
register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
end
device ref heci1 on
- # TODO Disable ME and HECI
register "HeciEnabled" = "1"
end
device ref uart2 on
diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
index cf0965b..c02a6ec 100644
--- a/src/mainboard/system76/gaze15/devicetree.cb
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -95,7 +95,7 @@
device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb
index 1362b3d..5c702b9 100644
--- a/src/mainboard/system76/lemp10/devicetree.cb
+++ b/src/mainboard/system76/lemp10/devicetree.cb
@@ -226,7 +226,6 @@
register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
end
device ref heci1 on
- # TODO Disable ME and HECI
register "HeciEnabled" = "1"
end
device ref uart2 on
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb
index 5648ca8..00d3708 100644
--- a/src/mainboard/system76/lemp9/devicetree.cb
+++ b/src/mainboard/system76/lemp9/devicetree.cb
@@ -102,7 +102,7 @@
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb
index b55cbbe..bb75616 100644
--- a/src/mainboard/system76/oryp5/devicetree.cb
+++ b/src/mainboard/system76/oryp5/devicetree.cb
@@ -108,7 +108,7 @@
device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb
index 8fc274b..85b5d26 100644
--- a/src/mainboard/system76/oryp6/devicetree.cb
+++ b/src/mainboard/system76/oryp6/devicetree.cb
@@ -110,7 +110,7 @@
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
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Change subject: soc/mediatek/mt8186: Add NOR-Flash support
......................................................................
Patch Set 3:
(1 comment)
File src/soc/mediatek/mt8186/Kconfig:
https://review.coreboot.org/c/coreboot/+/58837/comment/40a98af1_dce6bb2b
PS3, Line 19: config FLASH_DUAL_READ
i guess this is about the dual io read mode? if that's the case, maybe rename this to FLASH_DUAL_IO_READ, since that makes it at least for me clearer what this is about. or instead change it the help text to "dual IO read mode"? it's the same on all other existing mediatek socs, so i'll submit this patch as it is right now, but might be good to address this for all mediatek socs in a follow-up commit
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Change subject: amdfwtool: Set soc name for Stoneyridge
......................................................................
Patch Set 5:
(1 comment)
File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/58555/comment/f49b7c56_4233c926
PS5, Line 150: --soc-name "Stoneyridge" \
not 100% sure, but this might need to depend on FIRMWARE_TYPE; see my comment on CB:55454
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Change subject: amdfwtool: Fill PSP directory to ROMSIG based on the SOC ID
......................................................................
Patch Set 14:
(1 comment)
File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/55454/comment/e435ab9e_a243ef40
PS14, Line 127:
: ifeq ($(FIRMWARE_TYPE),ST)
: OPT_COMBOCAPABLE=--combo-capable
: endif
so does only stoneyridge/praeriefalcon use the new psp directory, but merlinfalcon still uses the old one?
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Change subject: amdfwtool: Add support for AMD's BIOS A/B recovery feature
......................................................................
Patch Set 26:
(7 comments)
Patchset:
PS26:
haven't completely reviewed everything in this patch yet, but it's probably better when i already post the comments on what i've found so far.
have you verified that a timeless build will result in identical images for a kahlee/grunt, a zork and a guybrush chromebook?
File util/amdfwtool/amdfwtool.h:
https://review.coreboot.org/c/coreboot/+/56773/comment/6358cd6e_1c45192d
PS26, Line 240: uint8_t recovery_ab;
i'd use a boolean here; probably also the case for some of the struct elements above
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/56773/comment/230ddeac_7e0dedf3
PS26, Line 669: int
this is a different type compared to cb_config->recovery_ab
https://review.coreboot.org/c/coreboot/+/56773/comment/ffe7186e_a992f77c
PS26, Line 1351: psp_directory_table *pspdir, *pspdir2 = NULL, *pspdir2_b = NULL;
maybe put the 3 definitions on 3 separate lines
https://review.coreboot.org/c/coreboot/+/56773/comment/c5c428d7_c299c722
PS26, Line 1700: pspdir2_b = NULL; /* More explicitly */
since the corresponding if block has curly braces, please also use curly braces around the one statement in the else branch
https://review.coreboot.org/c/coreboot/+/56773/comment/b72077ec_65b9dbb1
PS26, Line 1707: 0
NULL
https://review.coreboot.org/c/coreboot/+/56773/comment/f0dc4245_2ab09257
PS26, Line 1733: , *biosdir2_b = NULL
i'd put this second definition on a new line to make it more obvious what's done here
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