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Change subject: sc7280: Add support for USB
......................................................................
Patch Set 33: Code-Review+2
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Change subject: soc/qualcomm/common/usb: Add support for common USB driver
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Patch Set 33: Code-Review+2
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Change subject: qualcomm/sc7280: gpio: Support eGPIO scheme
......................................................................
Patch Set 2:
(4 comments)
File src/soc/qualcomm/common/gpio.c:
https://review.coreboot.org/c/coreboot/+/58580/comment/24c62d53_78c58362
PS2, Line 21: if ((read32(®s->cfg) >> GPIO_EGPIO_SHFT) & GPIO_EGPIO_BMSK)
Seem like we can just add it to the condition above. Something like:
| (read32(®s->cfg) & GPIO_EGPIO_BMSK) << GPIO_EGPIO_SHFT)
Then you don't need to define EGPIO_CFG_EN and just make some adjustments on GPIO_EGPIO_SHFT and GPIO_EGPIO_BMSK values appropriately.
File src/soc/qualcomm/common/include/soc/gpio_common.h:
https://review.coreboot.org/c/coreboot/+/58580/comment/6afdb280_e0e6b33d
PS2, Line 24: GPIO_EGPIO_BMSK
GPIO_CFG_EGPIO_BMSK?
https://review.coreboot.org/c/coreboot/+/58580/comment/c91cd060_44dbf8e6
PS2, Line 39: GPIO_EGPIO_SHFT
GPIO_CFG_EGPIO_SHFT?
https://review.coreboot.org/c/coreboot/+/58580/comment/85c909ef_931dfbd8
PS2, Line 87: enum egpio_cfg {
Is the plan to add more fields in here in the future? Just curious why we have an enum for 1 type.
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Change subject: amdfwtool: Change the definition of level to a bitwise form
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File util/amdfwtool/amdfwtool.h:
https://review.coreboot.org/c/coreboot/+/58765/comment/256d476f_56ab7bbf
PS2, Line 186: #define BDT_LVL1 0x1
for consistency it might be good to write this as (0x1 << 0). same below. i'd also drop the 0x prefix and just use (1 << 0) and (1 << 1)
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Change subject: amdfwtool: Extract out-of-bounds check to a function and move
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/58764/comment/bec876c2_6c6049a2
PS2, Line 358: ASSERT_FW_ENTRY
since this is a function and not a macro, i'd use a lower case function name here
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Change subject: amdfwtool: Use relative address for EFS gen2
......................................................................
Patch Set 15:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56438/comment/77d97530_f9c90498
PS2, Line 9: The second generation EFS (offset 0x24[0]=0) uses
: "binary relative" offsets and not "x86 physical
: MMIO address" like gen1.
:
: Chips like Cezanne can run in both cases, so no problem
: comes up so far.
:
: TODO: Need to fix the problem in psp_verstage.
> We still need to wait until the PSP verstage is signed and signed verstage is landed in the downstre […]
ok, then lets wait until the signed verstage binary with the fix to support relative addresses has landed
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Change subject: mb/purism/librem_skl: Clean up hda_verb.c
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
oh, wait, i mixed up 12AM and 12PM and submitted this patch series a bit too early. at least now i found out that i can switch gerrit to the 24h time format instead and the patch series wasn't something i consider possibly controversial
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