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Change subject: amdfwtool: Call the set_efs_table for Stoneyridge
......................................................................
Patch Set 3:
(2 comments)
File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/58871/comment/8795eedd_d1c9c313
PS3, Line 136: OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag)
i don't see the micron flag in the documentation for the pre-zen socs, so it's probably not needed to pass that parameter
https://review.coreboot.org/c/coreboot/+/58871/comment/fe0a842e_3992bd7d
PS3, Line 155: $(OPT_EFS_SPI_MICRON_FLAG) \
same comment as above
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Change subject: amdfwtool: Set soc name for Stoneyridge
......................................................................
Patch Set 5:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/58555/comment/25e1aa57_cda87be6
PS5, Line 1587: if (soc_id != PLATFORM_STONEYRIDGE) {
> do we need this special case for stoneyridge? set_efs_table has a case for stoneyrige, so i guess th […]
ok, the next patch removes the special case
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Change subject: amdfwtool: Set soc name for Stoneyridge
......................................................................
Patch Set 5:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/58555/comment/cb75b56a_2e541067
PS5, Line 1587: if (soc_id != PLATFORM_STONEYRIDGE) {
do we need this special case for stoneyridge? set_efs_table has a case for stoneyrige, so i guess that it should work, but would still be good to verify that it'll work
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Change subject: Herobrine: sc7280: Add support for audio
......................................................................
Patch Set 20:
(3 comments)
File src/mainboard/google/herobrine/board.h:
https://review.coreboot.org/c/coreboot/+/57449/comment/f581f01c_fc65fce1
PS20, Line 33:
one more tab
File src/mainboard/google/herobrine/chromeos.c:
https://review.coreboot.org/c/coreboot/+/57449/comment/3807b359_18c75f63
PS20, Line 19: gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP);
TPM configuration should be in a separate CL
https://review.coreboot.org/c/coreboot/+/57449/comment/7e817ead_d2b79bd6
PS20, Line 32: {GPIO_H1_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_H1_AP_INT),
Same comment as above.
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Change subject: mb/mainboard/herobrine: Initialize SPI FW for EC and TPM
......................................................................
Patch Set 84:
(1 comment)
File src/mainboard/google/herobrine/Kconfig:
https://review.coreboot.org/c/coreboot/+/50581/comment/fc1d9518_32547f69
PS84, Line 66: default 0xC if BOARD_GOOGLE_HEROBRINE
I think that this should never be true?
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Change subject: sc7280: Add support for USB
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Patch Set 33: Code-Review+2
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Change subject: soc/qualcomm/common/usb: Add support for common USB driver
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Patch Set 33: Code-Review+2
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